2017-11-08 19:47:45 +08:00
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/*
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2019-07-19 20:54:36 +08:00
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* Copyright (c) 2006-2019, RT-Thread Development Team
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2017-11-08 19:47:45 +08:00
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*
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2019-07-19 20:54:36 +08:00
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* SPDX-License-Identifier: Apache-2.0
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2017-11-08 19:47:45 +08:00
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*
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* Change Logs:
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* Date Author Notes
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2019-07-19 20:54:36 +08:00
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* 2016-09-07 Urey first version
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2017-11-08 19:47:45 +08:00
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*/
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#ifndef __ASSEMBLY__
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2019-07-19 20:46:06 +08:00
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#define __ASSEMBLY__
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2017-11-08 19:47:45 +08:00
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#endif
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#include "../common/mips.h"
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#define IRQ_STACK_SIZE 0x2000
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#define EXC_STACK_SIZE 0x2000
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.section ".bss"
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ALIGN(4)
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irq_stack_low:
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.space IRQ_STACK_SIZE
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irq_stack_top:
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.space 8
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ALIGN(4)
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exc_stack_low:
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.space EXC_STACK_SIZE
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exc_stack_top:
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.space 8
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#define SYSTEM_STACK 0x80003fe8
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;/*********************************************************************************************************
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; <20><><EFBFBD><EFBFBD>
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;*********************************************************************************************************/
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.global rtthread_startup
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.global mips_vfp32_init
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.global _start
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.section ".start", "ax"
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.set noreorder
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_start:
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.set noreorder
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la ra, _start
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li t1, 0x00800000
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mtc0 t1, CP0_CAUSE
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/* init cp0 registers. */
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li t0, 0x1000FC00 /* BEV = 0 and mask all interrupt */
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mtc0 t0, CP0_STATUS
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#ifdef __mips_hard_float
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jal mips_vfp32_init
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nop
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#endif
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/* setup stack pointer */
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li sp, SYSTEM_STACK
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la gp, _gp
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_cache_init:
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/* init caches, assumes a 4way * 128set * 32byte I/D cache */
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mtc0 zero, CP0_TAGLO /* TAGLO reg */
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mtc0 zero, CP0_TAGHI /* TAGHI reg */
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li t0, 3 /* enable cache for kseg0 accesses */
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mtc0 t0, CP0_CONFIG /* CONFIG reg */
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la t0, 0x80000000 /* an idx op should use an unmappable address */
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ori t1, t0, 0x4000 /* 16kB cache */
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_cache_loop:
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cache 0x8, 0(t0) /* index store icache tag */
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cache 0x9, 0(t0) /* index store dcache tag */
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bne t0, t1, _cache_loop
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addiu t0, t0, 0x20 /* 32 bytes per cache line */
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nop
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/* invalidate BTB */
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mfc0 t0, CP0_CONFIG
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nop
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ori t0, 2
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mtc0 t0, CP0_CONFIG
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nop
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/* jump to RT-Thread RTOS */
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jal rtthread_startup
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nop
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/* restart, never die */
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j _start
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nop
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.set reorder
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;/*********************************************************************************************************
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; <20>쳣<EFBFBD><ECB3A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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;*********************************************************************************************************/
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/* 0x0 - TLB refill handler */
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.section .vectors.1, "ax", %progbits
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j mips_tlb_refill_entry
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nop
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/* 0x100 - Cache error handler */
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.section .vectors.2, "ax", %progbits
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j mips_cache_error_entry
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nop
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/* 0x180 - Exception/Interrupt handler */
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.section .vectors.3, "ax", %progbits
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j mips_exception_entry
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nop
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/* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
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.section .vectors.4, "ax", %progbits
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j mips_interrupt_entry
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nop
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.section .vectors, "ax", %progbits
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.global mips_exception_handler
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// .global mips_syscall
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LEAF(mips_exception_entry)
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.set push
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.set noat
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.set noreorder
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.set volatile
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mfc0 k0, C0_CAUSE
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andi k0, k0, 0x7c
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beq zero, k0, except_do_intr
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nop
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andi k0,(0x08 << 2)
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beq zero,k0,except_do
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nop
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except_do_intr:
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la k0,mips_interrupt_entry
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jr k0
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nop
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except_do_syscall:
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// la k0,mips_syscall
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// jr k0
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nop
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except_do:
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//save sp
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move k0,sp
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//la sp, exc_stack_top
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subu sp, sp, CONTEXT_SIZE
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//save context
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sw $0, (4*0)(sp);
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sw $1, (4*1)(sp);
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sw $2, (4*2)(sp);
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sw $3, (4*3)(sp);
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sw $4, (4*4)(sp);
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sw $5, (4*5)(sp);
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sw $6, (4*6)(sp);
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sw $7, (4*7)(sp);
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sw $8, (4*8)(sp);
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sw $9, (4*9)(sp);
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sw $10, (4*10)(sp);
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sw $11, (4*11)(sp);
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sw $12, (4*12)(sp);
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sw $13, (4*13)(sp);
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sw $14, (4*14)(sp);
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sw $15, (4*15)(sp);
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sw $16, (4*16)(sp);
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sw $17, (4*17)(sp);
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sw $18, (4*18)(sp);
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sw $19, (4*19)(sp);
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sw $20, (4*20)(sp);
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sw $21, (4*21)(sp);
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sw $22, (4*22)(sp);
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sw $23, (4*23)(sp);
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sw $24, (4*24)(sp);
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sw $25, (4*25)(sp);
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sw $26, (4*26)(sp);
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sw $27, (4*27)(sp);
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sw $28, (4*28)(sp);
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sw k0, (4*29)(sp); //old sp
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sw $30, (4*30)(sp);
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sw $31, (4*31)(sp);
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/* STATUS CAUSE EPC.... */
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mfc0 $2, CP0_STATUS
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sw $2, STK_OFFSET_SR(sp)
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mfc0 $2, CP0_CAUSE
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sw $2, STK_OFFSET_CAUSE(sp)
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mfc0 $2, CP0_BADVADDR
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sw $2, STK_OFFSET_BADVADDR(sp)
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MFC0 $2, CP0_EPC
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sw $2, STK_OFFSET_EPC(sp)
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mfhi $2
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sw $2, STK_OFFSET_HI(sp)
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mflo $2
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sw $2, STK_OFFSET_LO(sp)
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move a0, sp
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la k0, mips_exception_handler
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j k0
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nop
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//
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.set pop
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END(mips_exception_entry)
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.global mips_tlb_refill_handler
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LEAF(mips_tlb_refill_entry)
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.set push
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.set noat
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.set noreorder
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.set volatile
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la k0,mips_tlb_refill_handler
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jr k0
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nop
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eret
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nop
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.set pop
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END(mips_tlb_refill_entry)
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.global mips_cache_error_handler
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LEAF(mips_cache_error_entry)
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.set push
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.set noat
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.set noreorder
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.set volatile
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la k0,mips_cache_error_handler
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jr k0
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nop
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eret
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nop
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.set pop
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END(mips_cache_error_entry)
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.global rt_interrupt_dispatch
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.global rt_interrupt_enter
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.global rt_interrupt_leave
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LEAF(mips_interrupt_entry)
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.set push
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.set noat
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.set noreorder
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.set volatile
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//mfc0 k0,CP0_EPC
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SAVE_CONTEXT
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mfc0 t0, CP0_CAUSE
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mfc0 t1, CP0_STATUS
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and t0, t1
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andi t0, 0xff00
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beqz t0, spurious_interrupt
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nop
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/* let k0 keep the current context sp */
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move k0, sp
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/* switch to kernel stack */
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la sp, irq_stack_top
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jal rt_interrupt_enter
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nop
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jal rt_interrupt_dispatch
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nop
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jal rt_interrupt_leave
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nop
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/* switch sp back to thread's context */
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move sp, k0
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/*
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* if rt_thread_switch_interrupt_flag set, jump to
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* rt_hw_context_switch_interrupt_do and don't return
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*/
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la k0, rt_thread_switch_interrupt_flag
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lw k1, 0(k0)
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beqz k1, spurious_interrupt
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nop
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sw zero, 0(k0) /* clear flag */
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nop
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/*
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* switch to the new thread
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*/
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la k0, rt_interrupt_from_thread
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lw k1, 0(k0)
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nop
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sw sp, 0(k1) /* store sp in preempted tasks's TCB */
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la k0, rt_interrupt_to_thread
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lw k1, 0(k0)
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nop
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lw sp, 0(k1) /* get new task's stack pointer */
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j spurious_interrupt
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nop
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|
|
spurious_interrupt:
|
|
|
|
|
|
RESTORE_CONTEXT
|
|
|
|
|
|
|
|
|
|
|
|
.set pop
|
|
|
|
|
|
END(mips_interrupt_entry)
|
