377 lines
11 KiB
C
377 lines
11 KiB
C
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/*
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* Copyright (C) 2012, Freescale Semiconductor, Inc. All Rights Reserved
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* THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
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* BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
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* Freescale Semiconductor, Inc.
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*/
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/*!
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* @file plat_startup.inc
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* @brief This file contains start-up DCD.
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*
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* @ingroup diag_init
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*/
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/* *INDENT-OFF* */
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#ifndef _PLAT_STARTUP_H_
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#define _PLAT_STARTUP_H_
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#include "soc_memory_map.h"
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#define IMAGE_ENTRY_ADDR 0x80000000
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#define IMAGE_SIZE 4*1024*1024
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#define L2CC_REG1_CTRL 0x00A02100
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#define L2CC_INV_REG 0x00A0277C
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#define L2CC_TAG_RAM_CTRL 0x00A02108
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#define L2CC_DAT_RAM_CTRL 0x00A0210C
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#define L2CC_PREFETCH_CTRL 0x00A02F60
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#define ROM_API_TABLE_BASE_ADDR (0x00000180)
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#define ROM_API_HWCNFG_SETUP_OFFSET (0x08)
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#define PLATFORM_INIT plat_dcd_startup
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#define ASM_REG32_WR(i, addr, val) \
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ldr r0, =addr; \
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ldr r1, =val; \
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str r1, [r0];
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// image starts at 0x00907000
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//flash header & DCD @ 0x400
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.macro plat_dcd_startup
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b startup
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.org 0x400
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/* First IVT to copy the plugin that initializes the system into OCRAM */
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ivt_header: .long 0x402000D1 //Tag=0xD1, Len=0x0020, Ver=0x40
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app_code_jump_v: .long 0x00907458 // Plugin entry point, address after the second IVT table
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reserv1: .long 0x0
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dcd_ptr: .long 0x0
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boot_data_ptr: .long 0x00907420
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self_ptr: .long 0x00907400
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app_code_csf: .long 0x0 // reserve 4K for csf
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reserv2: .long 0x0
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boot_data: .long 0x00907000
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image_len: .long 16*1024
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plugin: .long 0x1 // Enable plugin flag
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/* Second IVT to give entry point into the bootloader copied to DDR */
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ivt2_header: .long 0x402000D1 //Tag=0xD1, Len=0x0020, Ver=0x40
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app2_code_jump_v: .long startup // Entry point for the bootloader
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reserv3: .long 0x0
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dcd2_ptr: .long 0x0
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boot_data2_ptr: .long boot_data2
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self_ptr2: .long ivt2_header
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app_code_csf2: .long 0x0 // reserve 4K for csf
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reserv4: .long 0x0
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boot_data2: .long IMAGE_ENTRY_ADDR
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image_len2: .long IMAGE_SIZE
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plugin2: .long 0x0
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// Here starts the plugin code
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plugin_start:
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// Save the return address and the function arguments
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push {r0-r4, lr}
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#if defined(EVB) || defined(SABRE_LITE)
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ASM_REG32_WR(0, 0x020bc000, 0x30)
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ASM_REG32_WR(0, 0x020c4068, 0xffffffff)
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ASM_REG32_WR(0, 0x020c406c, 0xffffffff)
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ASM_REG32_WR(0, 0x020c4070, 0xffffffff)
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ASM_REG32_WR(0, 0x020c4074, 0xffffffff)
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ASM_REG32_WR(0, 0x020c4078, 0xffffffff)
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ASM_REG32_WR(0, 0x020c407c, 0xffffffff)
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ASM_REG32_WR(0, 0x020c4080, 0xffffffff)
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ASM_REG32_WR(0, 0x020c4084, 0xffffffff)
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ASM_REG32_WR(0, 0x020E04B4, 0x000C0000)
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ASM_REG32_WR(0, 0x020E04AC, 0x00000000)
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ASM_REG32_WR(0, 0x020E027C, 0x00000030)
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ASM_REG32_WR(0, 0x020E0250, 0x00000030)
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ASM_REG32_WR(0, 0x020E024C, 0x00000030)
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ASM_REG32_WR(0, 0x020E0490, 0x00000030)
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ASM_REG32_WR(0, 0x020E0288, 0x00000030)
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ASM_REG32_WR(0, 0x020E0270, 0x00000000)
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ASM_REG32_WR(0, 0x020E0260, 0x00000030)
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ASM_REG32_WR(0, 0x020E0264, 0x00000030)
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ASM_REG32_WR(0, 0x020E04A0, 0x00000030)
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ASM_REG32_WR(0, 0x020E0494, 0x00020000)
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ASM_REG32_WR(0, 0x020E0280, 0x00000030)
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ASM_REG32_WR(0, 0x020E0284, 0x00000030)
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ASM_REG32_WR(0, 0x020E04B0, 0x00020000)
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ASM_REG32_WR(0, 0x020E0498, 0x00000030)
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ASM_REG32_WR(0, 0x020E04A4, 0x00000030)
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ASM_REG32_WR(0, 0x020E0244, 0x00000030)
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ASM_REG32_WR(0, 0x020E0248, 0x00000030)
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ASM_REG32_WR(0, 0x021B001C, 0x00008000)
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ASM_REG32_WR(0, 0x021B0800, 0xA1390003)
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ASM_REG32_WR(0, 0x021B080C, 0x001b001E)
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ASM_REG32_WR(0, 0x021B083C, 0x42400240)
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ASM_REG32_WR(0, 0x021B0848, 0x00003A3E)
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ASM_REG32_WR(0, 0x021B0850, 0x00003230)
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ASM_REG32_WR(0, 0x021B081C, 0x33333333)
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ASM_REG32_WR(0, 0x021B0820, 0x33333333)
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ASM_REG32_WR(0, 0x021B082C, 0xf3333333)
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ASM_REG32_WR(0, 0x021B0830, 0xf3333333)
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ASM_REG32_WR(0, 0x021B08C0, 0x00922012)
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ASM_REG32_WR(0, 0x021B08b8, 0x00000800)
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ASM_REG32_WR(0, 0x021B0004, 0x0002002D)
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ASM_REG32_WR(0, 0x021B0008, 0x1B333000)
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ASM_REG32_WR(0, 0x021B000C, 0x676B54B3)
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ASM_REG32_WR(0, 0x021B0010, 0xB68E0A83)
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ASM_REG32_WR(0, 0x021B0014, 0x01FF00DB)
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ASM_REG32_WR(0, 0x021B0018, 0x00211740)
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ASM_REG32_WR(0, 0x021B001C, 0x00008000)
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ASM_REG32_WR(0, 0x021B002C, 0x000026D2)
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ASM_REG32_WR(0, 0x021B0030, 0x006C1023)
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ASM_REG32_WR(0, 0x021B0040, 0x0000005F)
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ASM_REG32_WR(0, 0x021B0000, 0x85180000)
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ASM_REG32_WR(0, 0x021B001C, 0x02008032)
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ASM_REG32_WR(0, 0x021B001C, 0x00008033)
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ASM_REG32_WR(0, 0x021B001C, 0x00048031)
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ASM_REG32_WR(0, 0x021B001C, 0x15208030)
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ASM_REG32_WR(0, 0x021B001C, 0x04008040)
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ASM_REG32_WR(0, 0x021B0020, 0x00000800)
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ASM_REG32_WR(0, 0x021B0818, 0x00000227)
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ASM_REG32_WR(0, 0x021B0004, 0x0002552D)
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ASM_REG32_WR(0, 0x021B0404, 0x00011006)
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ASM_REG32_WR(0, 0x021B001C, 0x00000000)
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#else
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#error "Please add the DDR initialization code for this board, unless you can make sure the existing code can be shared."
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#endif
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read_obds:
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/********************
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The following is to fill in those arguments for this ROM function
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pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
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This function is used to copy data from the storage media into DDR.
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start - Initial (possibly partial) image load address on entry. Final image load address on exit.
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bytes - Initial (possibly partial) image size on entry. Final image size on exit.
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boot_data - Initial @ref ivt Boot Data load address.
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*/
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adr r0, DDR_DEST_ADDR
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adr r1, COPY_SIZE
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adr r2, BOOT_DATA
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/*
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* check the _pu_irom_api_table for the address
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*/
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before_calling_rom___pu_irom_hwcnfg_setup:
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//mov r4, #0x2000
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//add r4, r4, #0xed
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//blx r4 // This address might change in future ROM versions.
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ldr r3, =ROM_API_TABLE_BASE_ADDR /* Address of rom_api_table is 0xc0 */
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ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET] /* hwcnfg setup function address is 3rd entry in the api table address 0xc8 */
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blx r4 /* call into ROM function */
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after_calling_rom___pu_irom_hwcnfg_setup:
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/* SDRAM has been setup, binary image has been copied to SDRAM */
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b startup // Jump to our code directly
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DDR_DEST_ADDR: .word IMAGE_ENTRY_ADDR
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COPY_SIZE: .word IMAGE_SIZE
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BOOT_DATA: .word IMAGE_ENTRY_ADDR
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.word IMAGE_SIZE //real data to be copied by the pu_irom_hwcnfg_setup()
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.word 0
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.endm //plat_dcd_startup
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// #define PLATFORM_ASM_STARTUP platform_asm_startup
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.macro platform_asm_startup
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config_L2_cache:
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disable_L2_cache
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init_aips_start:
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init_aips
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init_reloc_start:
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/* Check if need to copy image to Redboot ROM space */
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ldr r0, =0xFFFFF000
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and r0, r0, pc
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ldr r1, =IMAGE_ENTRY_ADDR
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cmp r0, r1
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beq skip_SDRAM_copy
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add r2, r0, #IMAGE_SIZE
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1: ldmia r0!, {r3-r10}
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stmia r1!, {r3-r10}
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cmp r0, r2
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ble 1b
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/* Jump to SDRAM */
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ldr r1, =0xFFFF
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and r0, pc, r1 /* offset of pc */
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ldr r1, =(IMAGE_ENTRY_ADDR + 0x8)
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add pc, r0, r1
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nop
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nop
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nop
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nop
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skip_SDRAM_copy:
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.endm //platform_asm_startup
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/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
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.macro init_aips
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/*
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* not forced to user-mode.
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*/
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ldr r0, =AIPS_TZ1_BASE_ADDR
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ldr r1, =0x77777777
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str r1, [r0, #0x00]
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str r1, [r0, #0x04]
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ldr r0, =AIPS_TZ2_BASE_ADDR
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str r1, [r0, #0x00]
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str r1, [r0, #0x04]
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.endm /* init_aips */
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.macro clean_L1_DCache
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mov r0, #0
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mcr p15, 2, r0, c0, c0, 0 // select DCache
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mrc p15, 1, r0, c0, c0, 0 // read CCSIDR
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mov r0, r0, ASR #13
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ldr r3, =0x3FFF
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and r0, r0, r3
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cmp r0, #0x7F
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moveq r6, #0x1000 // 4KB * 4way = 16KB
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beq clean_and_invalidate_L1_dcache
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cmp r0, #0xFF
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moveq r6, #0x2000 // 32KB
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beq clean_and_invalidate_L1_dcache
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movne r6, #0x4000 // 64KB
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clean_and_invalidate_L1_dcache:
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mov r2, #0x00000000
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mov r3, #0x40000000
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mov r4, #0x80000000
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mov r5, #0xC0000000
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clean_and_invalidate_L1_dcache_byset:
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mcr p15, 0, r2, c7, c14, 2 //clean and invalidate dcache on way 0
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mcr p15, 0, r3, c7, c14, 2 //clean and invalidate dcache on way 1
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mcr p15, 0, r4, c7, c14, 2 //clean and invalidate dcache on way 2
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mcr p15, 0, r5, c7, c14, 2 //clean and invalidate dcache on way 3
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add r2, r2, #0x20
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add r3, r3, #0x20
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add r4, r4, #0x20
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add r5, r5, #0x20
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cmp r2, r6
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bne clean_and_invalidate_L1_dcache_byset
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.endm
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.macro enable_L1_cache
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 6 // invalidate BTAC
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mcr p15, 0, r0, c7, c5, 0 // invalidate icache
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mov r0, #0
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mcr p15, 2, r0, c0, c0, 0 // select DCache
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mrc p15, 1, r0, c0, c0, 0 // read CCSIDR
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mov r0, r0, ASR #13
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ldr r3, =0x3FFF
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and r0, r0, r3
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cmp r0, #0x7F
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moveq r6, #0x1000 // 4KB * 4way = 16KB
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beq invalidate_dcache
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cmp r0, #0xFF
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moveq r6, #0x2000 // 32KB
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beq invalidate_dcache
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movne r6, #0x4000 // 64KB
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invalidate_dcache:
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mov r2, #0x00000000
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mov r3, #0x40000000
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mov r4, #0x80000000
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mov r5, #0xC0000000
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invalidate_dcache_byset:
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mcr p15, 0, r2, c7, c6, 2 //invalidate dcache on way 0
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mcr p15, 0, r3, c7, c6, 2 //invalidate dcache on way 1
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mcr p15, 0, r4, c7, c6, 2 //invalidate dcache on way 2
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mcr p15, 0, r5, c7, c6, 2 //invalidate dcache on way 3
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add r2, r2, #0x20
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add r3, r3, #0x20
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add r4, r4, #0x20
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add r5, r5, #0x20
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cmp r2, r6
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bne invalidate_dcache_byset
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ldr r0, =0x00930000 //where to store the TLB page table
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mcr p15, 0, r0, c2, c0, 0
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ldr r0, =0x55555555
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mcr p15, 0, r0, c3, c0, 0
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mrc p15, 0, r0, c1, c0, 0 // read CP15 register 1 into r0
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|
orr r0, r0, #(0x1<<12) // enable I Cache
|
||
|
|
orr r0, r0, #(0x1<<11) // turn on BP
|
||
|
|
orr r0, r0, #(0x1<<2) // enable D Cache
|
||
|
|
/*Attention: If you want to enable MMU, must set up the TLB tables first!!*/
|
||
|
|
bic r0, r0, #(0x1<<0) // disable MMU
|
||
|
|
mcr p15, 0, r0, c1, c0, 0 // write CP15 register 1
|
||
|
|
.endm
|
||
|
|
|
||
|
|
.macro disable_L1_cache
|
||
|
|
mrc p15, 0, r0, c1, c0, 0
|
||
|
|
bic r0, r0, #(0x1<<12)
|
||
|
|
bic r0, r0, #(0x1<<11)
|
||
|
|
bic r0, r0, #(0x1<<2)
|
||
|
|
bic r0, r0, #(0x1<<0)
|
||
|
|
mcr p15, 0, r0, c1, c0, 0
|
||
|
|
.endm
|
||
|
|
|
||
|
|
.macro disable_L1_DCache
|
||
|
|
mrc p15, 0, r0, c1, c0, 0
|
||
|
|
ands r0, r0, #(0x1<<11) //check if L1 DCache has been disabled
|
||
|
|
beq disable_L1_DCache_done
|
||
|
|
bic r0, r0, #(0x1<<11)
|
||
|
|
bic r0, r0, #(0x1<<0) //disable MMU
|
||
|
|
mcr p15, 0, r0, c1, c0, 0
|
||
|
|
clean_L1_DCache
|
||
|
|
disable_L1_DCache_done:
|
||
|
|
.endm
|
||
|
|
|
||
|
|
.macro enable_L2_cache
|
||
|
|
/* set latency: 4x cycles read, 2x cycles write, (3x cycles setup)*/
|
||
|
|
ldr r1,= L2CC_TAG_RAM_CTRL
|
||
|
|
ldr r0,=0x0132
|
||
|
|
str r0,[r1]
|
||
|
|
ldr r1, =L2CC_DAT_RAM_CTRL
|
||
|
|
ldr r0,=0x0132
|
||
|
|
str r0,[r1]
|
||
|
|
|
||
|
|
/* invalidate L2Cache by way */
|
||
|
|
ldr r1, =L2CC_INV_REG
|
||
|
|
ldr r0, =0xffff
|
||
|
|
str r0,[r1]
|
||
|
|
l2cc_inv_done:
|
||
|
|
ldr r2,[r1]
|
||
|
|
mov r0,#0x0
|
||
|
|
cmp r2,r0
|
||
|
|
bne l2cc_inv_done
|
||
|
|
|
||
|
|
/* turn on l2 cache */
|
||
|
|
ldr r1, =L2CC_REG1_CTRL
|
||
|
|
mov r0,#1
|
||
|
|
str r0,[r1]
|
||
|
|
.endm
|
||
|
|
|
||
|
|
.macro disable_L2_cache
|
||
|
|
ldr r1, =L2CC_REG1_CTRL
|
||
|
|
mov r0,#0
|
||
|
|
str r0,[r1]
|
||
|
|
.endm
|
||
|
|
|
||
|
|
#endif //_PLAT_STARTUP_H_
|