261 lines
8.4 KiB
C
261 lines
8.4 KiB
C
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/*
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* This file is part of FH8620 BSP for RT-Thread distribution.
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*
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* Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
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* All rights reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Visit http://www.fullhan.com to get contact with Fullhan.
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*
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* Change Logs:
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* Date Author Notes
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*/
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#include "inc/fh_driverlib.h"
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int I2C_WaitMasterIdle(struct fh_i2c_obj *i2c_obj)
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{
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UINT32 reg;
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int timeout = 200; //20 ms
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while (GET_REG(i2c_obj->base + OFFSET_I2C_STATUS) & DW_IC_STATUS_MASTER_ACTIVITY)
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{
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if(timeout < 0)
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{
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rt_kprintf( "ERROR: %s, timeout waiting for master not active, txflr: 0x%x, rxflr: 0x%x, stat: 0x%x\n",
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__func__, I2C_GetReceiveFifoLevel(i2c_obj), I2C_GetTransmitFifoLevel(i2c_obj), GET_REG(i2c_obj->base + OFFSET_I2C_INTR_STAT));
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return -RT_ETIMEOUT;
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}
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timeout--;
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udelay(100);
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}
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return 0;
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}
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int I2C_WaitDeviceIdle(struct fh_i2c_obj *i2c_obj)
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{
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UINT32 reg;
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int timeout = 2000; //200 ms
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while (GET_REG(i2c_obj->base + OFFSET_I2C_STATUS) & DW_IC_STATUS_ACTIVITY)
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{
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if(timeout < 0)
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{
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rt_kprintf( "ERROR: %s, timeout waiting for device not active\n", __func__);
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return -RT_ETIMEOUT;
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}
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timeout--;
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udelay(100);
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}
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return 0;
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}
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static inline UINT32 I2C_CalcSclHcnt(UINT32 ic_clk, UINT32 tSYMBOL, UINT32 tf, int cond, int offset)
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{
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/*
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* DesignWare I2C core doesn't seem to have solid strategy to meet
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* the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec
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* will result in violation of the tHD;STA spec.
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*/
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if (cond)
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/*
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* Conditional expression:
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*
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* IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
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*
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* This is based on the DW manuals, and represents an ideal
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* configuration. The resulting I2C bus speed will be
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* faster than any of the others.
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*
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* If your hardware is free from tHD;STA issue, try this one.
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*/
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return (ic_clk * tSYMBOL + 5000) / 10000 - 8 + offset;
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else
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/*
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* Conditional expression:
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*
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* IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
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*
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* This is just experimental rule; the tHD;STA period turned
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* out to be proportinal to (_HCNT + 3). With this setting,
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* we could meet both tHIGH and tHD;STA timing specs.
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*
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* If unsure, you'd better to take this alternative.
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*
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* The reason why we need to take into account "tf" here,
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* is the same as described in i2c_fh_scl_lcnt().
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*/
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return (ic_clk * (tSYMBOL + tf) + 5000) / 10000 - 3 + offset;
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}
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static inline UINT32 I2C_CalcSclLcnt(UINT32 ic_clk, UINT32 tLOW, UINT32 tf, int offset)
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{
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/*
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* Conditional expression:
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*
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* IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
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*
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* DW I2C core starts counting the SCL CNTs for the LOW period
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* of the SCL clock (tLOW) as soon as it pulls the SCL line.
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* In order to meet the tLOW timing spec, we need to take into
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* account the fall time of SCL signal (tf). Default tf value
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* should be 0.3 us, for safety.
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*/
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return ((ic_clk * (tLOW + tf) + 5000) / 10000) - 1 + offset;
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}
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static int I2C_SetSpeedCount(struct fh_i2c_obj *i2c_obj)
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{
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UINT32 hcnt, lcnt;
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/* set standard and fast speed count for high/low periods */
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/* Standard-mode */
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hcnt = I2C_CalcSclHcnt(i2c_obj->input_clock,
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40, /* tHD;STA = tHIGH = 4.0 us */
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3, /* tf = 0.3 us */
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0, /* 0: DW default, 1: Ideal */
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0); /* No offset */
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lcnt = I2C_CalcSclLcnt(i2c_obj->input_clock,
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47, /* tLOW = 4.7 us */
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3, /* tf = 0.3 us */
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0); /* No offset */
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SET_REG(i2c_obj->base + OFFSET_I2C_SS_SCL_HCNT, hcnt);
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SET_REG(i2c_obj->base + OFFSET_I2C_SS_SCL_LCNT, lcnt);
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/* Fast-mode */
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hcnt = I2C_CalcSclHcnt(i2c_obj->input_clock,
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6, /* tHD;STA = tHIGH = 0.6 us */
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3, /* tf = 0.3 us */
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0, /* 0: DW default, 1: Ideal */
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0); /* No offset */
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lcnt = I2C_CalcSclLcnt(i2c_obj->input_clock,
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13, /* tLOW = 1.3 us */
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3, /* tf = 0.3 us */
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0); /* No offset */
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SET_REG(i2c_obj->base + OFFSET_I2C_FS_SCL_HCNT, hcnt);
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SET_REG(i2c_obj->base + OFFSET_I2C_FS_SCL_LCNT, lcnt);
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return 0;
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}
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UINT32 I2C_ClearAndGetInterrupts(struct fh_i2c_obj *i2c_obj)
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{
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UINT32 stat;
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/*
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* The IC_INTR_STAT register just indicates "enabled" interrupts.
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* Ths unmasked raw version of interrupt status bits are available
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* in the IC_RAW_INTR_STAT register.
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*
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* That is,
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* stat = readl(IC_INTR_STAT);
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* equals to,
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* stat = readl(IC_RAW_INTR_STAT) & readl(IC_INTR_MASK);
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*
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* The raw version might be useful for debugging purposes.
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*/
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stat = GET_REG(i2c_obj->base + OFFSET_I2C_INTR_STAT);
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/*
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* Do not use the IC_CLR_INTR register to clear interrupts, or
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* you'll miss some interrupts, triggered during the period from
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* readl(IC_INTR_STAT) to readl(IC_CLR_INTR).
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*
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* Instead, use the separately-prepared IC_CLR_* registers.
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*/
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if (stat & DW_IC_INTR_RX_UNDER)
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GET_REG(i2c_obj->base + OFFSET_I2C_CLR_RX_UNDER);
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if (stat & DW_IC_INTR_RX_OVER)
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GET_REG(i2c_obj->base + OFFSET_I2C_CLR_RX_OVER);
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if (stat & DW_IC_INTR_TX_OVER)
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GET_REG(i2c_obj->base + OFFSET_I2C_CLR_TX_OVER);
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if (stat & DW_IC_INTR_RD_REQ)
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GET_REG(i2c_obj->base + OFFSET_I2C_CLR_RD_REQ);
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if (stat & DW_IC_INTR_TX_ABRT)
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{
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/*
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* The IC_TX_ABRT_SOURCE register is cleared whenever
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* the IC_CLR_TX_ABRT is read. Preserve it beforehand.
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*/
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i2c_obj->abort_source = GET_REG(i2c_obj->base + OFFSET_I2C_TX_ABRT_SOURCE);
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GET_REG(i2c_obj->base + OFFSET_I2C_CLR_TX_ABRT);
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}
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if (stat & DW_IC_INTR_RX_DONE)
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GET_REG(i2c_obj->base + OFFSET_I2C_CLR_RX_DONE);
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if (stat & DW_IC_INTR_ACTIVITY)
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GET_REG(i2c_obj->base + OFFSET_I2C_CLR_ACTIVITY);
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if (stat & DW_IC_INTR_STOP_DET)
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GET_REG(i2c_obj->base + OFFSET_I2C_CLR_STOP_DET);
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if (stat & DW_IC_INTR_START_DET)
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GET_REG(i2c_obj->base + OFFSET_I2C_CLR_START_DET);
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if (stat & DW_IC_INTR_GEN_CALL)
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GET_REG(i2c_obj->base + OFFSET_I2C_CLR_GEN_CALL);
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return stat;
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}
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int I2C_HandleTxAbort(struct fh_i2c_obj *i2c_obj)
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{
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unsigned long abort_source = i2c_obj->abort_source;
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int i;
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if (abort_source & DW_IC_TX_ABRT_NOACK)
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{
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//for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
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// rt_kprintf( "%s: %s\n", __func__, abort_sources[i]);
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return 0;
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}
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//for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
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// rt_kprintf( "%s: %s\n", __func__, abort_sources[i]);
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rt_kprintf("%s: abort_sources 0x%x\n", __func__, abort_sources);
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if (abort_source & DW_IC_TX_ARB_LOST)
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return 0;
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else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
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return 0; /* wrong msgs[] data */
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else
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return 0;
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}
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void I2C_Init(struct fh_i2c_obj *i2c_obj)
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{
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UINT32 ic_con;
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UINT32 param0 = GET_REG(i2c_obj->base + OFFSET_I2C_COMP_PARAM1);
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I2C_WaitMasterIdle(i2c_obj);
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I2C_Enable(i2c_obj, RT_FALSE);
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I2C_SetSpeedCount(i2c_obj);
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i2c_obj->config.tx_fifo_depth = ((param0 >> 16) & 0xff) + 1;
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i2c_obj->config.rx_fifo_depth = ((param0 >> 8) & 0xff) + 1;
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/* Configure Tx/Rx FIFO threshold levels */
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SET_REG(i2c_obj->base + OFFSET_I2C_TX_TL, i2c_obj->config.tx_fifo_depth - 1);
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SET_REG(i2c_obj->base + OFFSET_I2C_RX_TL, 0);
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/* configure the i2c master */
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ic_con = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE |
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/*OFFSET_I2C_CON_RESTART_EN |*/ DW_IC_CON_SPEED_FAST; //DW_IC_CON_SPEED_STD;
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SET_REG( i2c_obj->base + OFFSET_I2C_CON, ic_con);
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}
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