474 lines
12 KiB
C
474 lines
12 KiB
C
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/*
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* Copyright (c) 2006-2019, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-07-29 zdzn first version
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*/
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#include "raspi.h"
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#include "drv_gpio.h"
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#ifdef BSP_USING_PIN
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struct rpi_pin_index
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{
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rt_uint8_t phy_id;
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rt_uint8_t bcm_id;
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rt_uint8_t signal_name;
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rt_uint8_t magic;
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};
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//raspi phy id and bcm id
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static struct rpi_pin_index phypin_index[] =
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{
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{0, 0, 0, 0},
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{1, 0, 0, 0},
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{2, 0, 0, 0},
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{3, BCM_GPIO_PIN_2, RPI_SDA1, PIN_MAGIC},
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{4, 0, 0, 0},
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{5, BCM_GPIO_PIN_3, RPI_SCL1, PIN_MAGIC},
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{6, 0, 0, 0},
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{7, BCM_GPIO_PIN_4, RPI_GPIO_GCLK, PIN_MAGIC},
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{8, BCM_GPIO_PIN_14, RPI_TXD0, PIN_MAGIC},
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{9, 0, 0, 0},
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{10, BCM_GPIO_PIN_15, RPI_RXD0, PIN_MAGIC},
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{11, BCM_GPIO_PIN_17, RPI_GPIO_GEN0, PIN_MAGIC},
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{12, BCM_GPIO_PIN_18, RPI_GPIO_GEN1, PIN_MAGIC},
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{13, BCM_GPIO_PIN_27, RPI_GPIO_GEN2, PIN_MAGIC},
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{14, 0, 0, 0},
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{15, BCM_GPIO_PIN_22, RPI_GPIO_GEN3, PIN_MAGIC},
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{16, BCM_GPIO_PIN_23, RPI_GPIO_GEN4, PIN_MAGIC},
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{17, 0, 0, 0},
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{18, BCM_GPIO_PIN_24, RPI_GPIO_GEN5, PIN_MAGIC},
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{19, BCM_GPIO_PIN_10, RPI_SPI_MOSI, PIN_MAGIC},
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{20, 0, 0, 0},
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{21, BCM_GPIO_PIN_9, RPI_SPI_MISO, PIN_MAGIC},
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{22, BCM_GPIO_PIN_25, RPI_GPIO_GEN6, PIN_MAGIC},
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{23, BCM_GPIO_PIN_11, RPI_SPI_SCLK, PIN_MAGIC},
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{24, BCM_GPIO_PIN_8, RPI_SPI_CE0_N, PIN_MAGIC},
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{25, 0, 0, 0},
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{26, BCM_GPIO_PIN_7, RPI_SPI_CE1_N, PIN_MAGIC},
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{27, BCM_GPIO_PIN_0, RPI_SDA0, PIN_MAGIC},
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{28, BCM_GPIO_PIN_1, RPI_SCL0, PIN_MAGIC},
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{29, BCM_GPIO_PIN_5, RPI_CAM_CLK, PIN_MAGIC},
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{30, 0, 0, 0},
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{31, BCM_GPIO_PIN_6, RPI_LAN_RUN, PIN_MAGIC},
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{32, BCM_GPIO_PIN_12, 0, PIN_MAGIC},
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{33, BCM_GPIO_PIN_13, 0, PIN_MAGIC},
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{34, 0, 0, 0},
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{35, BCM_GPIO_PIN_19, 0, PIN_MAGIC},
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{36, BCM_GPIO_PIN_16, RPI_STATUS_LED_N, PIN_MAGIC},
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{37, BCM_GPIO_PIN_26, 0, PIN_MAGIC},
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{38, BCM_GPIO_PIN_20, 0, PIN_MAGIC},
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{39, 0, 0, 0},
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{40, BCM_GPIO_PIN_21, RPI_CAM_GPIO, PIN_MAGIC},
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};
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/*
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* gpio_int[0] for BANK0 (pins 0-27)
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* gpio_int[1] for BANK1 (pins 28-45)
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* gpio_int[2] for BANK2 (pins 46-53)
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*/
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static struct gpio_irq_def _g_gpio_irq_tbl[GPIO_IRQ_NUM];
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int gpio_set_func(enum gpio_code code, enum bcm_gpio_pin pin, rt_uint8_t func)
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{
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RT_ASSERT((GPIO_CODE_PHY <= code) && (code < GPIO_CODE_NUM));
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RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_53));
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if (func & 0x8)
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{
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rt_kprintf("[line]:%d There is a warning with parameter input", __LINE__);
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return RT_EINVAL;
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}
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switch(func)
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{
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case 0x00:
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bcm283x_gpio_fsel(pin, BCM283X_GPIO_FSEL_OUTP);
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break;
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case 0x01:
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bcm283x_gpio_fsel(pin, BCM283X_GPIO_FSEL_INPT);
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break;
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case 0x02:
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bcm283x_gpio_set_pud(pin, BCM283X_GPIO_PUD_UP);
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bcm283x_gpio_fsel(pin, BCM283X_GPIO_FSEL_INPT);
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break;
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case 0x03:
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bcm283x_gpio_set_pud(pin, BCM283X_GPIO_PUD_DOWN);
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bcm283x_gpio_fsel(pin, BCM283X_GPIO_FSEL_INPT);
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break;
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case 0x04:
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bcm283x_gpio_set_pud(pin, BCM283X_GPIO_PUD_OFF);
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bcm283x_gpio_fsel(pin, BCM283X_GPIO_FSEL_OUTP);
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break;
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}
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return RT_EOK;
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}
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int gpio_set_value(enum gpio_code code, enum bcm_gpio_pin pin, rt_uint8_t value)
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{
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RT_ASSERT((GPIO_CODE_PHY <= code) && (code < GPIO_CODE_NUM));
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RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_53));
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if (value & 0xE)
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{
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rt_kprintf("[line]:%d There is a warning with parameter input", __LINE__);
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return RT_EINVAL;
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}
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bcm283x_gpio_write(pin, value);
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return RT_EOK;
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}
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int gpio_get_value(enum gpio_code code, enum bcm_gpio_pin pin)
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{
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rt_uint8_t data;
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RT_ASSERT((GPIO_CODE_PHY <= code) && (code < GPIO_CODE_NUM));
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RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_53));
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data = bcm283x_gpio_lev(pin);
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return data;
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}
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void gpio_set_irq_callback(enum gpio_code port, enum bcm_gpio_pin pin, void (*irq_cb)(void *), void *irq_arg)
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{
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RT_ASSERT((GPIO_CODE_PHY < port) && (port < GPIO_CODE_NUM));
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RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_53));
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rt_uint8_t index;
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if (pin <= 27)
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{
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index = 0;
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}
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else if (pin <= 45)
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{
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index = 1;
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}
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else{
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index = 2;
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}
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_g_gpio_irq_tbl[index].irq_cb[pin] = irq_cb;
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_g_gpio_irq_tbl[index].irq_arg[pin] = irq_arg;
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}
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void gpio_set_irq_type(enum gpio_code port, enum bcm_gpio_pin pin, rt_uint8_t irq_type)
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{
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RT_ASSERT((GPIO_CODE_PHY < port) && (port < GPIO_CODE_NUM));
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RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_53));
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rt_uint8_t index;
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if (pin <= 27)
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{
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index = 0;
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}
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else if (pin <= 45)
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{
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index = 1;
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}
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else{
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index = 2;
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}
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_g_gpio_irq_tbl[index].irq_type[pin] = irq_type;
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switch(irq_type)
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{
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case 0x00:
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bcm283x_gpio_ren(pin);
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break;
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case 0x01:
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bcm283x_gpio_fen(pin);
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break;
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case 0x02:
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bcm283x_gpio_aren(pin);
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bcm283x_gpio_afen(pin);
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break;
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case 0x03:
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bcm283x_gpio_hen(pin);
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break;
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case 0x04:
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bcm283x_gpio_len(pin);
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break;
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}
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}
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static void gpio_ack_irq(int irq, enum bcm_gpio_pin pin)
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{
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rt_uint32_t data;
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data = IRQ_PEND2;
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data &= (0x0 << (irq - 32));
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IRQ_PEND2 = data;
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data = IRQ_DISABLE2;
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data |= (0x1 << (irq - 32));
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IRQ_DISABLE2 = data;
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}
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void gpio_irq_disable(enum gpio_code port, enum bcm_gpio_pin pin)
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{
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rt_uint8_t index;
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int irq = 0;
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RT_ASSERT((GPIO_CODE_PHY < port) && (port < GPIO_CODE_NUM));
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RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_53));
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if (pin <= 27)
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{
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index = 0;
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irq = IRQ_GPIO0;
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}else if (pin <= 45){
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index = 1;
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irq = IRQ_GPIO1;
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}else{
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index = 2;
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irq = IRQ_GPIO2;
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}
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gpio_ack_irq(irq, pin);
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rt_uint8_t irq_type = _g_gpio_irq_tbl[index].irq_type[pin];
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switch(irq_type)
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{
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case 0x00:
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bcm283x_gpio_clr_ren(pin);
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break;
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case 0x01:
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bcm283x_gpio_clr_fen(pin);
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break;
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case 0x02:
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bcm283x_gpio_clr_aren(pin);
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bcm283x_gpio_clr_afen(pin);
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break;
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case 0x03:
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bcm283x_gpio_clr_hen(pin);
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break;
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case 0x04:
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bcm283x_gpio_clr_len(pin);
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break;
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}
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}
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void gpio_clear_irq_callback(enum gpio_code port, enum bcm_gpio_pin pin)
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{
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rt_uint8_t index;
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gpio_irq_disable(port, pin);
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if (pin <= 27)
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{
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index = 0;
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}
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else if (pin <= 45)
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{
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index = 1;
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}
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else
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{
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index = 2;
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}
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_g_gpio_irq_tbl[index].irq_cb[pin] = RT_NULL;
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_g_gpio_irq_tbl[index].irq_arg[pin] = RT_NULL;
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_g_gpio_irq_tbl[index].irq_type[pin] = RT_NULL;
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}
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void gpio_irq_enable(enum gpio_code port, enum bcm_gpio_pin pin)
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{
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rt_uint32_t offset;
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rt_uint32_t data;
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RT_ASSERT((GPIO_CODE_PHY < port) && (port < GPIO_CODE_NUM));
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RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_53));
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offset = pin;
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if (pin <= 27)
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{
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offset = IRQ_GPIO0 - 32;
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}
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else if (pin <= 45)
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{
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offset = IRQ_GPIO1 - 32;
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}
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else
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{
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offset = IRQ_GPIO2 - 32;
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}
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data = IRQ_ENABLE2;
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data |= 0x1 << offset;
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IRQ_ENABLE2 = data;
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}
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//gpio_int[0] for BANK0 (pins 0-27)
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//gpio_int[1] for BANK1 (pins 28-45)
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//gpio_int[2] for BANK2 (pins 46-53)
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static void gpio_irq_handler(int irq, void *param)
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{
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struct gpio_irq_def *irq_def = (struct gpio_irq_def *)param;
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rt_uint32_t pin;
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rt_uint32_t addr;
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rt_uint32_t value;
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rt_uint32_t tmpvalue;
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if (irq == IRQ_GPIO0)
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{
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/* 0~27 */
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addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPEDS0; // 0~31
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value = bcm283x_peri_read(addr);
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value &= 0x0fffffff;
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pin = 0;
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}
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else if (irq == IRQ_GPIO1)
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{
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/* 28-45 */
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addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPEDS0;
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tmpvalue = bcm283x_peri_read(addr);
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tmpvalue &= (~0x0fffffff);
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addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPEDS1;
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value = bcm283x_peri_read(addr);
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value &= 0x3fff;
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value = (value<<4) | tmpvalue;
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pin = 28;
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}
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else if (irq == IRQ_GPIO2)
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{
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/* 46-53 */
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addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPEDS1;
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value = bcm283x_peri_read(addr);
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value &= (~0x3fff);
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value &= 0xff600000;
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pin = 46;
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}
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bcm283x_peri_write(addr,0);
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while (value)
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{
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if ((value & 0x1) && (irq_def->irq_cb[pin] != RT_NULL))
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{
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irq_def->irq_cb[pin](irq_def->irq_arg[pin]);
|
||
|
|
gpio_ack_irq(irq,pin);
|
||
|
|
}
|
||
|
|
pin++;
|
||
|
|
value = value >> 1;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
|
||
|
|
{
|
||
|
|
if ((pin > PIN_NUM(phypin_index)) || (phypin_index[pin].magic != PIN_MAGIC))
|
||
|
|
{
|
||
|
|
rt_kprintf("pin:%d value wrongful", pin);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
gpio_set_func(GPIO_CODE_BCM, phypin_index[pin].bcm_id, mode);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value)
|
||
|
|
{
|
||
|
|
if ((pin > PIN_NUM(phypin_index)) || (phypin_index[pin].magic != PIN_MAGIC))
|
||
|
|
{
|
||
|
|
rt_kprintf("pin:%d value wrongful", pin);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
gpio_set_value(GPIO_CODE_BCM, phypin_index[pin].bcm_id, value);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int pin_read(struct rt_device *device, rt_base_t pin)
|
||
|
|
{
|
||
|
|
if ((pin > PIN_NUM(phypin_index)) || (phypin_index[pin].magic != PIN_MAGIC))
|
||
|
|
{
|
||
|
|
rt_kprintf("pin:%d value wrongful", pin);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
return gpio_get_value(GPIO_CODE_BCM, phypin_index[pin].bcm_id);
|
||
|
|
}
|
||
|
|
|
||
|
|
static rt_err_t pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args)
|
||
|
|
{
|
||
|
|
if ((pin > PIN_NUM(phypin_index)) || (phypin_index[pin].magic != PIN_MAGIC))
|
||
|
|
{
|
||
|
|
rt_kprintf("pin:%d value wrongful", pin);
|
||
|
|
return RT_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
gpio_set_irq_callback(GPIO_CODE_BCM , phypin_index[pin].bcm_id, hdr, args);
|
||
|
|
gpio_set_irq_type(GPIO_CODE_BCM, phypin_index[pin].bcm_id, mode);
|
||
|
|
|
||
|
|
return RT_EOK;
|
||
|
|
}
|
||
|
|
|
||
|
|
static rt_err_t pin_detach_irq(struct rt_device *device, rt_int32_t pin)
|
||
|
|
{
|
||
|
|
if ((pin > PIN_NUM(phypin_index)) || (phypin_index[pin].magic != PIN_MAGIC))
|
||
|
|
{
|
||
|
|
rt_kprintf("pin:%d value wrongful", pin);
|
||
|
|
return RT_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
gpio_clear_irq_callback(GPIO_CODE_BCM, phypin_index[pin].bcm_id);
|
||
|
|
|
||
|
|
return RT_EOK;
|
||
|
|
}
|
||
|
|
|
||
|
|
rt_err_t pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
|
||
|
|
{
|
||
|
|
if ((pin > PIN_NUM(phypin_index)) || (phypin_index[pin].magic != PIN_MAGIC))
|
||
|
|
{
|
||
|
|
rt_kprintf("pin:%d value wrongful", pin);
|
||
|
|
return RT_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (enabled)
|
||
|
|
gpio_irq_enable(GPIO_CODE_BCM, phypin_index[pin].bcm_id);
|
||
|
|
else
|
||
|
|
gpio_irq_disable(GPIO_CODE_BCM, phypin_index[pin].bcm_id);
|
||
|
|
|
||
|
|
return RT_EOK;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct rt_pin_ops ops =
|
||
|
|
{
|
||
|
|
pin_mode,
|
||
|
|
pin_write,
|
||
|
|
pin_read,
|
||
|
|
pin_attach_irq,
|
||
|
|
pin_detach_irq,
|
||
|
|
pin_irq_enable,
|
||
|
|
};
|
||
|
|
#endif
|
||
|
|
|
||
|
|
int rt_hw_gpio_init(void)
|
||
|
|
{
|
||
|
|
#ifdef BSP_USING_PIN
|
||
|
|
rt_device_pin_register("gpio", &ops, RT_NULL);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* install ISR */
|
||
|
|
rt_hw_interrupt_install(IRQ_GPIO0, gpio_irq_handler, &_g_gpio_irq_tbl[0], "gpio0_irq");
|
||
|
|
rt_hw_interrupt_umask(IRQ_GPIO0);
|
||
|
|
|
||
|
|
rt_hw_interrupt_install(IRQ_GPIO1, gpio_irq_handler, &_g_gpio_irq_tbl[1], "gpio1_irq");
|
||
|
|
rt_hw_interrupt_umask(IRQ_GPIO1);
|
||
|
|
|
||
|
|
rt_hw_interrupt_install(IRQ_GPIO2, gpio_irq_handler, &_g_gpio_irq_tbl[2], "gpio2_irq");
|
||
|
|
rt_hw_interrupt_umask(IRQ_GPIO2);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
INIT_DEVICE_EXPORT(rt_hw_gpio_init);
|