303 lines
8.6 KiB
C
303 lines
8.6 KiB
C
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/*
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* File : drv_spi.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2017 RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2017-06-05 tanek first implementation.
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* 2018-04-19 misonyo Porting for gd32f30x
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*/
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#include "drv_spi.h"
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#include "gd32f30x.h"
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#include <rtthread.h>
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#if defined(RT_USING_SPI) && defined(RT_USING_PIN)
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#include <rtdevice.h>
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#if !defined(RT_USING_SPI0) && !defined(RT_USING_SPI1) && \
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!defined(RT_USING_SPI2)
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#error "Please define at least one SPIx"
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#endif
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/* #define DEBUG */
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#ifdef DEBUG
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#define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__)
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#else
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#define DEBUG_PRINTF(...)
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#endif
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/* private rt-thread spi ops function */
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static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration);
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static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message);
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static struct rt_spi_ops gd32_spi_ops =
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{
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configure,
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xfer
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};
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static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration)
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{
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spi_parameter_struct spi_init_struct;
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rt_uint32_t spi_periph = (rt_uint32_t)device->bus->parent.user_data;
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(configuration != RT_NULL);
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if(configuration->data_width <= 8)
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{
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spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT;
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}
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else if(configuration->data_width <= 16)
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{
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spi_init_struct.frame_size = SPI_FRAMESIZE_16BIT;
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}
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else
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{
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return RT_EIO;
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}
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{
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rcu_clock_freq_enum spi_src;
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rt_uint32_t spi_apb_clock;
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rt_uint32_t max_hz;
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max_hz = configuration->max_hz;
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DEBUG_PRINTF("sys freq: %d\n", rcu_clock_freq_get(CK_SYS));
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DEBUG_PRINTF("CK_APB2 freq: %d\n", rcu_clock_freq_get(CK_APB2));
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DEBUG_PRINTF("max freq: %d\n", max_hz);
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if (spi_periph == SPI1 || spi_periph == SPI2)
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{
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spi_src = CK_APB1;
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}
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else
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{
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spi_src = CK_APB2;
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}
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spi_apb_clock = rcu_clock_freq_get(spi_src);
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if(max_hz >= spi_apb_clock/2)
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{
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spi_init_struct.prescale = SPI_PSC_2;
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}
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else if (max_hz >= spi_apb_clock/4)
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{
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spi_init_struct.prescale = SPI_PSC_4;
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}
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else if (max_hz >= spi_apb_clock/8)
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{
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spi_init_struct.prescale = SPI_PSC_8;
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}
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else if (max_hz >= spi_apb_clock/16)
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{
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spi_init_struct.prescale = SPI_PSC_16;
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}
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else if (max_hz >= spi_apb_clock/32)
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{
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spi_init_struct.prescale = SPI_PSC_32;
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}
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else if (max_hz >= spi_apb_clock/64)
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{
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spi_init_struct.prescale = SPI_PSC_64;
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}
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else if (max_hz >= spi_apb_clock/128)
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{
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spi_init_struct.prescale = SPI_PSC_128;
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}
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else
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{
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/* min prescaler 256 */
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spi_init_struct.prescale = SPI_PSC_256;
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}
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} /* baudrate */
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switch(configuration->mode & RT_SPI_MODE_3)
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{
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case RT_SPI_MODE_0:
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spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE;
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break;
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case RT_SPI_MODE_1:
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spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_2EDGE;
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break;
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case RT_SPI_MODE_2:
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spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_1EDGE;
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break;
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case RT_SPI_MODE_3:
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spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE;
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break;
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}
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/* MSB or LSB */
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if(configuration->mode & RT_SPI_MSB)
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{
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spi_init_struct.endian = SPI_ENDIAN_MSB;
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}
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else
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{
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spi_init_struct.endian = SPI_ENDIAN_LSB;
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}
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spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX;
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spi_init_struct.device_mode = SPI_MASTER;
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spi_init_struct.nss = SPI_NSS_SOFT;
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spi_init(spi_periph, &spi_init_struct);
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spi_crc_off(spi_periph);
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spi_enable(spi_periph);
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return RT_EOK;
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};
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static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message)
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{
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rt_base_t gd32_cs_pin = (rt_base_t)device->parent.user_data;
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rt_uint32_t spi_periph = (rt_uint32_t)device->bus->parent.user_data;
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struct rt_spi_configuration * config = &device->config;
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RT_ASSERT(device != NULL);
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RT_ASSERT(message != NULL);
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/* take CS */
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if(message->cs_take)
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{
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rt_pin_write(gd32_cs_pin, PIN_LOW);
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DEBUG_PRINTF("spi take cs\n");
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}
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{
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if(config->data_width <= 8)
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{
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const rt_uint8_t * send_ptr = message->send_buf;
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rt_uint8_t * recv_ptr = message->recv_buf;
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rt_uint32_t size = message->length;
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DEBUG_PRINTF("spi poll transfer start: %d\n", size);
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while(size--)
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{
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rt_uint8_t data = 0xFF;
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if(send_ptr != RT_NULL)
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{
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data = *send_ptr++;
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}
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// Todo: replace register read/write by gd32f3 lib
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//Wait until the transmit buffer is empty
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while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE));
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// Send the byte
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spi_i2s_data_transmit(spi_periph, data);
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//Wait until a data is received
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while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE));
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// Get the received data
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data = spi_i2s_data_receive(spi_periph);
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if(recv_ptr != RT_NULL)
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{
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*recv_ptr++ = data;
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}
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}
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DEBUG_PRINTF("spi poll transfer finsh\n");
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}
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else if(config->data_width <= 16)
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{
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const rt_uint16_t * send_ptr = message->send_buf;
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rt_uint16_t * recv_ptr = message->recv_buf;
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rt_uint32_t size = message->length;
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while(size--)
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{
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rt_uint16_t data = 0xFF;
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if(send_ptr != RT_NULL)
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{
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data = *send_ptr++;
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}
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//Wait until the transmit buffer is empty
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while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE));
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// Send the byte
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spi_i2s_data_transmit(spi_periph, data);
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//Wait until a data is received
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while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE));
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// Get the received data
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data = spi_i2s_data_receive(spi_periph);
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if(recv_ptr != RT_NULL)
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{
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*recv_ptr++ = data;
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}
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}
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}
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}
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/* release CS */
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if(message->cs_release)
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{
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rt_pin_write(gd32_cs_pin, PIN_HIGH);
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DEBUG_PRINTF("spi release cs\n");
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}
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return message->length;
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};
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int gd32_hw_spi_init(void)
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{
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int result = 0;
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#ifdef RT_USING_SPI0
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static struct rt_spi_bus spi_bus0;
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spi_bus0.parent.user_data = (void *)SPI0;
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result = rt_spi_bus_register(&spi_bus0, "spi0", &gd32_spi_ops);
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rcu_periph_clock_enable(RCU_GPIOA);
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rcu_periph_clock_enable(RCU_SPI0);
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/* SPI0_SCK(PA5), SPI0_MISO(PA6) and SPI0_MOSI(PA7) GPIO pin configuration */
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gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_5 | GPIO_PIN_7);
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gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_6);
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#endif
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#ifdef RT_USING_SPI1
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static struct rt_spi_bus spi_bus1;
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spi_bus1.parent.user_data = (void *)SPI1;
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result = rt_spi_bus_register(&spi_bus1, "spi1", &gd32_spi_ops);
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rcu_periph_clock_enable(RCU_SPI1);
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rcu_periph_clock_enable(RCU_GPIOB);
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/* SPI1_SCK(PB13), SPI1_MISO(PB14) and SPI1_MOSI(PB15) GPIO pin configuration */
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gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_13 | GPIO_PIN_15);
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gpio_init(GPIOB, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_14);
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#endif
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#ifdef RT_USING_SPI2
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static struct rt_spi_bus spi_bus2;
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spi_bus2.parent.user_data = (void *)SPI2;
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result = rt_spi_bus_register(&spi_bus2, "spi2", &gd32_spi_ops);
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rcu_periph_clock_enable(RCU_SPI2);
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rcu_periph_clock_enable(RCU_GPIOB);
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/* SPI2_SCK(PB3), SPI2_MISO(PB4) and SPI2_MOSI(PB5) GPIO pin configuration */
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gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_3 | GPIO_PIN_5);
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gpio_init(GPIOB, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_4);
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#endif
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return result;
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}
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INIT_BOARD_EXPORT(gd32_hw_spi_init);
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#endif
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