322 lines
8.8 KiB
C
322 lines
8.8 KiB
C
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/* ------------------------------------------
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* Copyright (c) 2016, Synopsys, Inc. All rights reserved.
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1) Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* \version 2016.05
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* \date 2014-07-15
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* \author Wayne Ren(Wei.Ren@synopsys.com)
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--------------------------------------------- */
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/**
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* \file
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* \ingroup ARC_HAL_MISC_CACHE
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* \brief header file of cache module
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*/
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#ifndef _ARC_HAL_CACHE_H_
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#define _ARC_HAL_CACHE_H_
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#include "inc/embARC_toolchain.h"
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#include "inc/arc/arc.h"
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#include "inc/arc/arc_builtin.h"
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#include "inc/arc/arc_exception.h"
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/**
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* \name instruction cache control register related definition
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* \todo this definitions will be reviewed.
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* @{
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*/
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#define IC_CTRL_IC_ENABLE 0x0 /*!< enable instruction cache */
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#define IC_CTRL_IC_DISABLE 0x1 /*!< disable instruction cache */
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#define IC_CTRL_DIRECT_ACCESS 0x0 /*!< direct access mode */
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#define IC_CTRL_INDIRECT_ACCESS 0x20 /*!< indirect access mode */
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#define IC_CTRL_OP_SUCCEEDED 0x8 /*!< instruction cache operation succeeded */
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/** @} */
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/**
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* \name data cache control register related definition
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* \todo this definition will be reviewed.
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* @{
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*/
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#define IC_CTRL_I
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#define DC_CTRL_DC_ENABLE 0x0 /*!< enable data cache */
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#define DC_CTRL_DC_DISABLE 0x1 /*!< disable data cache */
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#define DC_CTRL_INVALID_ONLY 0x0 /*!< invalid data cache only */
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#define DC_CTRL_INVALID_FLUSH 0x40 /*!< invalid and flush data cache */
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#define DC_CTRL_ENABLE_FLUSH_LOCKED 0x80 /*!< the locked data cache can be flushed */
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#define DC_CTRL_DISABLE_FLUSH_LOCKED 0x0 /*!< the locked data cache cannot be flushed */
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#define DC_CTRL_FLUSH_STATUS 0x100 /*!< flush status */
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#define DC_CTRL_DIRECT_ACCESS 0x0 /*!< direct access mode */
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#define DC_CTRL_INDIRECT_ACCESS 0x20 /*!< indirect access mode */
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#define DC_CTRL_OP_SUCCEEDED 0x4 /*!< data cache operation succeeded */
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/** @} */
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/**
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* \name instruction cache related inline function
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* @{
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*/
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/**
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* \brief check whether instruction cache is available,
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* 0 for not available, >0 for available
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*/
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Inline uint8_t icache_available(void)
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{
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return (_arc_aux_read(AUX_BCR_I_CACHE) & 0xF);
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}
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/**
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* \brief enable instruction cache
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* \param[in] icache_en_mask operation mask
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*/
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Inline void icache_enable(uint32_t icache_en_mask)
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{
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if (!icache_available()) return;
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_arc_aux_write(AUX_IC_CTRL, icache_en_mask);
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}
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/**
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* \brief disable instruction cache
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*/
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Inline void icache_disable(void)
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{
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if (!icache_available()) return;
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_arc_aux_write(AUX_IC_CTRL, IC_CTRL_IC_DISABLE);
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}
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/**
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* \brief invalidate the entire instruction cache
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*/
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Inline void icache_invalidate(void)
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{
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if (!icache_available()) return;
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/* invalidate the entire icache */
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_arc_aux_write(AUX_IC_IVIC, 0);
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Asm("nop_s");
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Asm("nop_s");
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Asm("nop_s");
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}
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/**
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* \brief invalidate specific cache line
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* \param[in] address memory address
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*/
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Inline void icache_invalidate_line(uint32_t address)
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{
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if (!icache_available()) return;
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_arc_aux_write(AUX_IC_IVIL, address);
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/* the 3 nops are required by ARCv2 ISA */
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Asm("nop_s");
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Asm("nop_s");
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Asm("nop_s");
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}
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/**
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* \brief lock specific cache line
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* \param[in] address memory address
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* \return 0, succeeded, -1, failed
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*/
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Inline int32_t icache_lock_line(uint32_t address)
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{
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if (!icache_available()) return -1;
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_arc_aux_write(AUX_IC_LIL, address);
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if(_arc_aux_read(AUX_IC_CTRL) & IC_CTRL_OP_SUCCEEDED) {
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return 0;
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} else {
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return -1;
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}
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}
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/**
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* \brief set icache access mode
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* \param[in] mode, access mode, 1: indirect access 0:direct access
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*/
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Inline void icache_access_mode(uint32_t mode)
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{
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if (!icache_available()) return;
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if (mode) {
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_arc_aux_write(AUX_IC_CTRL, _arc_aux_read(AUX_IC_CTRL) | IC_CTRL_INDIRECT_ACCESS);
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} else {
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_arc_aux_write(AUX_IC_CTRL, _arc_aux_read(AUX_IC_CTRL) & (~IC_CTRL_INDIRECT_ACCESS));
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}
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}
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/** @} */
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/**
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* \name data cache related inline functions
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* @{
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*/
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/**
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* \brief check whether data cache is available,
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* 0 for not available, >0 for available
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*/
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Inline uint8_t dcache_available(void)
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{
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return (_arc_aux_read(AUX_BCR_D_CACHE) & 0xF);
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}
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/**
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* \brief invalidate the entire data cache
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*/
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Inline void dcache_invalidate(void)
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{
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if (!dcache_available()) return;
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uint32_t status;
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status = cpu_lock_save();
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_arc_aux_write(AUX_DC_IVDC, 1);
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/* wait for flush completion */
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while (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS);
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cpu_unlock_restore(status);
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}
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/**
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* \brief invalidate the specific cache line
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* \param[in] address memory address
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*/
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Inline void dcache_invalidate_line(uint32_t address)
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{
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if (!dcache_available()) return;
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_arc_aux_write(AUX_DC_IVDL, address);
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Asm("nop_s");
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Asm("nop_s");
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Asm("nop_s");
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}
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/**
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* \brief enable data cache
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* \param[in] dcache_en_mask operation mask
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*/
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Inline void dcache_enable(uint32_t dcache_en_mask)
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{
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if (!dcache_available()) return;
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_arc_aux_write(AUX_DC_CTRL, dcache_en_mask);
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}
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/**
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* \brief disable data cache
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*/
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Inline void dcache_disable(void)
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{
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if (!dcache_available()) return;
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_arc_aux_write(AUX_DC_CTRL, DC_CTRL_DC_DISABLE);
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}
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/**
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* \brief flush data cache
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*/
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Inline void dcache_flush(void)
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{
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if (!dcache_available()) return;
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uint32_t status;
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status = cpu_lock_save();
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_arc_aux_write(AUX_DC_FLSH, 1);
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/* wait for flush completion */
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while (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS);
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cpu_unlock_restore(status);
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}
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/**
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* \brief flush the specific data cache line
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* \param[in] address memory address
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*/
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Inline void dcache_flush_line(uint32_t address)
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{
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if (!dcache_available()) return;
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uint32_t status;
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status = cpu_lock_save();
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_arc_aux_write(AUX_DC_FLDL, address);
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while (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS);
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cpu_unlock_restore(status);
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}
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/**
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* \brief lock the specific data cache line
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* \param[in] address memory address
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* \return 0, succeeded, -1, failed
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*/
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Inline int dcache_lock_line(uint32_t address)
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{
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if (!dcache_available()) return -1;
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_arc_aux_write(AUX_DC_LDL, address);
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if(_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_OP_SUCCEEDED) {
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return 0;
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} else {
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return -1;
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}
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}
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/**
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* \brief set dcache access mode
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* \param[in] mode, access mode, 1: indirect access 0:direct access
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*/
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Inline void dcache_access_mode(uint32_t mode)
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{
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if (!dcache_available()) return;
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if (mode) {
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_arc_aux_write(AUX_DC_CTRL, _arc_aux_read(AUX_DC_CTRL) | DC_CTRL_INDIRECT_ACCESS);
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} else {
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_arc_aux_write(AUX_DC_CTRL, _arc_aux_read(AUX_DC_CTRL) & (~DC_CTRL_INDIRECT_ACCESS));
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}
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}
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/** @} */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* \name declarations of cache related functions
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* @{
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*/
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extern int32_t icache_invalidate_mlines(uint32_t start_addr, uint32_t size);
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extern int32_t icache_lock_mlines(uint32_t start_addr, uint32_t size);
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extern int32_t icache_direct_write(uint32_t cache_addr, uint32_t tag, uint32_t data);
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extern int32_t icache_direct_read(uint32_t cache_addr, uint32_t *tag, uint32_t *data);
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extern int32_t icache_indirect_read(uint32_t mem_addr, uint32_t *tag, uint32_t *data);
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extern int32_t dcache_invalidate_mlines(uint32_t start_addr, uint32_t size);
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extern int32_t dcache_flush_mlines(uint32_t start_addr, uint32_t size);
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extern int32_t dcache_lock_mlines(uint32_t start_addr, uint32_t size);
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extern int32_t dcache_direct_write(uint32_t cache_addr, uint32_t tag, uint32_t data);
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extern int32_t dcache_direct_read(uint32_t cache_addr, uint32_t *tag, uint32_t *data);
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extern int32_t dcache_indirect_read(uint32_t mem_addr, uint32_t *tag, uint32_t *data);
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extern void arc_cache_init(void);
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#ifdef __cplusplus
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}
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#endif
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/** @} */
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#endif /* _ARC_HAL_CACHE_H_ */
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