338 lines
11 KiB
C
338 lines
11 KiB
C
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/*
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* File : core_ck802.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2017-01-01 Urey first version
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <stdint.h>
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#include <core_ck802.h>
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/* flag in interrupt handling */
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rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
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rt_uint32_t rt_thread_switch_interrupt_flag;
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/*******************************************************************************
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* Hardware Abstraction Layer
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Core Function Interface contains:
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- Core VIC Functions
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- Core CORET Functions
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- Core Register Access Functions
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******************************************************************************/
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/**
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\defgroup CSI_Core_FunctionInterface Functions and Instructions Reference
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*/
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/* ########################## NVIC functions #################################### */
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/**
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\ingroup CSI_Core_FunctionInterface
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\defgroup CSI_Core_NVICFunctions NVIC Functions
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\brief Functions that manage interrupts and exceptions via the NVIC.
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@{
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*/
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/* Interrupt Priorities are WORD accessible only under CSKYv6M */
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/* The following MACROS handle generation of the register offset and byte masks */
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#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
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#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
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static uint32_t s_nvic_prio_bits = __NVIC_PRIO_BITS;
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/**
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\brief initialize the NVIC interrupt controller
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\param [in] prio_bits the priority bits of NVIC interrupt controller.
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*/
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void drv_nvic_init(uint32_t prio_bits)
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{
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if (s_nvic_prio_bits >= 8U)
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{
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return;
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}
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s_nvic_prio_bits = prio_bits;
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}
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/**
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\brief Enable External Interrupt
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\details Enables a device-specific interrupt in the NVIC interrupt controller.
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\param [in] IRQn External interrupt number. Value cannot be negative.
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*/
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void drv_nvic_enable_irq(int32_t IRQn)
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{
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NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
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#ifdef CONFIG_SYSTEM_SECURE
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NVIC->ISSR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
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#endif
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}
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/**
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\brief Disable External Interrupt
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\details Disables a device-specific interrupt in the NVIC interrupt controller.
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\param [in] IRQn External interrupt number. Value cannot be negative.
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*/
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void drv_nvic_disable_irq(int32_t IRQn)
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{
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NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
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}
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/**
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\brief Enable External Secure Interrupt
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\details Enables a secure device-specific interrupt in the NVIC interrupt controller.
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\param [in] IRQn External interrupt number. Value cannot be negative.
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*/
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void drv_nvic_enable_sirq(int32_t IRQn)
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{
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NVIC->ISSR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
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}
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/**
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\brief Get Pending Interrupt
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\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
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\param [in] IRQn Interrupt number.
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\return 0 Interrupt status is not pending.
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\return 1 Interrupt status is pending.
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*/
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uint32_t drv_nvic_get_pending_irq(int32_t IRQn)
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{
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return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
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}
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/**
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\brief Set Pending Interrupt
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\details Sets the pending bit of an external interrupt.
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\param [in] IRQn Interrupt number. Value cannot be negative.
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*/
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void drv_nvic_set_pending_irq(int32_t IRQn)
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{
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NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
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}
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/**
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\brief Clear Pending Interrupt
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\details Clears the pending bit of an external interrupt.
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\param [in] IRQn External interrupt number. Value cannot be negative.
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*/
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void drv_nvic_clear_pending_irq(int32_t IRQn)
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{
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NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
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}
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/**
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\brief Get Wake up Interrupt
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\details Reads the wake up register in the NVIC and returns the pending bit for the specified interrupt.
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\param [in] IRQn Interrupt number.
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\return 0 Interrupt is not set as wake up interrupt.
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\return 1 Interrupt is set as wake up interrupt.
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*/
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uint32_t drv_nvic_get_wakeup_irq(int32_t IRQn)
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{
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return ((uint32_t)(((NVIC->IWER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
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}
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/**
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\brief Set Wake up Interrupt
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\details Sets the wake up bit of an external interrupt.
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\param [in] IRQn Interrupt number. Value cannot be negative.
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*/
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void drv_nvic_set_wakeup_irq(int32_t IRQn)
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{
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NVIC->IWER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
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}
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/**
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\brief Clear Wake up Interrupt
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\details Clears the wake up bit of an external interrupt.
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\param [in] IRQn External interrupt number. Value cannot be negative.
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*/
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void drv_nvic_clear_wakeup_irq(int32_t IRQn)
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{
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NVIC->IWDR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
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}
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/**
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\brief Get Active Interrupt
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\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
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\param [in] IRQn Device specific interrupt number.
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\return 0 Interrupt status is not active.
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\return 1 Interrupt status is active.
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\note IRQn must not be negative.
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*/
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uint32_t drv_nvic_get_active(int32_t IRQn)
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{
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return ((uint32_t)(((NVIC->IABR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
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}
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/**
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\brief Set Threshold register
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\details set the threshold register in the NVIC.
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\param [in] VectThreshold specific vecter threshold.
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\param [in] PrioThreshold specific priority threshold.
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*/
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void drv_nvic_set_threshold(uint32_t VectThreshold, uint32_t PrioThreshold)
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{
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NVIC->IPTR = 0x80000000 | (((VectThreshold + 32) & 0xFF) << 8) | ((PrioThreshold & 0x3) << 6);
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}
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/**
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\brief Set Interrupt Priority
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\details Sets the priority of an interrupt.
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\note The priority cannot be set for every core interrupt.
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\param [in] IRQn Interrupt number.
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\param [in] priority Priority to set.
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*/
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void drv_nvic_set_prio(int32_t IRQn, uint32_t priority)
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{
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NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
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(((priority << (8U - s_nvic_prio_bits)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
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}
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/**
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\brief Get Interrupt Priority
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\details Reads the priority of an interrupt.
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The interrupt number can be positive to specify an external (device specific) interrupt,
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or negative to specify an internal (core) interrupt.
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\param [in] IRQn Interrupt number.
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\return Interrupt Priority.
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Value is aligned automatically to the implemented priority bits of the microcontroller.
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*/
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uint32_t drv_nvic_get_prio(int32_t IRQn)
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{
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return ((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - s_nvic_prio_bits)));
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}
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/*@} end of CSI_Core_NVICFunctions */
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/* ################################## SysTick function ############################################ */
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/**
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\ingroup CSI_Core_FunctionInterface
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\defgroup CSI_Core_SysTickFunctions SysTick Functions
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\brief Functions that configure the System.
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@{
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*/
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/**
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\brief CORE timer Configuration
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\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
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Counter is in free running mode to generate periodic interrupts.
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\param [in] ticks Number of ticks between two interrupts.
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\param [in] IRQn core timer Interrupt number.
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\return 0 Function succeeded.
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\return 1 Function failed.
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\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
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function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
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must contain a vendor-specific implementation of this function.
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*/
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uint32_t drv_coret_config(uint32_t ticks, int32_t IRQn)
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{
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if ((ticks - 1UL) > CORET_LOAD_RELOAD_Msk)
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{
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return (1UL); /* Reload value impossible */
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}
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CORET->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
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drv_nvic_set_prio(IRQn, (1UL << s_nvic_prio_bits) - 1UL); /* set Priority for Systick Interrupt */
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CORET->VAL = 0UL; /* Load the CORET Counter Value */
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CORET->CTRL = CORET_CTRL_CLKSOURCE_Msk |
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CORET_CTRL_TICKINT_Msk |
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CORET_CTRL_ENABLE_Msk; /* Enable CORET IRQ and CORET Timer */
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return (0UL); /* Function successful */
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}
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/**
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\brief get CORE timer reload value
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\return CORE timer counter value.
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*/
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uint32_t drv_coret_get_load(void)
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{
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return CORET->LOAD;
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}
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/**
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\brief get CORE timer counter value
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\return CORE timer counter value.
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*/
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uint32_t drv_coret_get_value(void)
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{
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return CORET->VAL;
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}
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/*@} end of CSI_Core_SysTickFunctions */
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#if 0
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/* ##################################### DCC function ########################################### */
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/**
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\ingroup CSI_Core_FunctionInterface
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\defgroup CSI_core_DebugFunctions HAD Functions
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\brief Functions that access the HAD debug interface.
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@{
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*/
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/**
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\brief HAD Send Character
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\details Transmits a character via the HAD channel 0, and
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\li Just returns when no debugger is connected that has booked the output.
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\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
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\param [in] ch Character to transmit.
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\returns Character to transmit.
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*/
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uint32_t HAD_SendChar(uint32_t ch)
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{
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DCC->DERJR = (uint8_t)ch;
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return (ch);
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}
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/**
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\brief HAD Receive Character
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\details Inputs a character via the external variable \ref HAD_RxBuffer.
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\return Received character.
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\return -1 No character pending.
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*/
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int32_t HAD_ReceiveChar(void)
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{
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int32_t ch = -1; /* no character available */
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if (_FLD2VAL(DCC_EHSR_JW, DCC->EHSR))
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{
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ch = DCC->DERJW;
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}
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return (ch);
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}
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/**
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\brief HAD Check Character
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\details Checks whether a character is pending for reading in the variable \ref HAD_RxBuffer.
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\return 0 No character available.
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\return 1 Character available.
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*/
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int32_t HAD_CheckChar(void)
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{
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return _FLD2VAL(DCC_EHSR_JW, DCC->EHSR); /* no character available */
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}
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#endif
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