311 lines
12 KiB
C
311 lines
12 KiB
C
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/******************************************************************************
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* @file i2s.h
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* @version V0.10
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* $Revision: 12 $
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* $Date: 15/09/22 6:48p $
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* @brief NUC472/NUC442 I2S driver header file
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*
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* @note
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* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#ifndef __I2S_H__
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#define __I2S_H__
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#include "NUC472_442.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
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@{
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*/
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/** @addtogroup NUC472_442_I2S_Driver I2S Driver
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@{
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*/
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/** @addtogroup NUC472_442_I2S_EXPORTED_CONSTANTS I2S Exported Constants
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@{
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*/
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#define I2S_DATABIT_8 (0 << I2S_CTL_WDWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */
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#define I2S_DATABIT_16 (1 << I2S_CTL_WDWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */
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#define I2S_DATABIT_24 (2 << I2S_CTL_WDWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */
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#define I2S_DATABIT_32 (3 << I2S_CTL_WDWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */
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/* Audio Format */
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#define I2S_MONO I2S_CTL_MONO_Msk /*!< Mono channel \hideinitializer */
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#define I2S_STEREO 0 /*!< Stereo channel \hideinitializer */
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/* I2S Data Format */
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#define I2S_FORMAT_MSB I2S_CTL_FORMAT_Msk /*!< MSB data format \hideinitializer */
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#define I2S_FORMAT_I2S 0 /*!< I2S data format \hideinitializer */
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#define I2S_FORMAT_PCMB I2S_CTL_FORMAT_Msk /*!< PCMB data format \hideinitializer */
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#define I2S_FORMAT_PCMA 0 /*!< PCMA data format \hideinitializer */
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/* I2S Interface */
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#define I2S_PCM I2S_CTL_PCMEN_Msk /*!< PCM interface is selected \hideinitializer */
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#define I2S_I2S 0 /*!< I2S interface is selected \hideinitializer */
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/* I2S Operation mode */
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#define I2S_MODE_SLAVE I2S_CTL_SLAVE_Msk /*!< As slave mode \hideinitializer */
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#define I2S_MODE_MASTER 0 /*!< As master mode \hideinitializer */
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/* I2S FIFO Threshold */
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#define I2S_FIFO_TX_LEVEL_WORD_0 0 /*!< TX threshold is 0 word \hideinitializer */
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#define I2S_FIFO_TX_LEVEL_WORD_1 (1 << I2S_CTL_TXTH_Pos) /*!< TX threshold is 1 word \hideinitializer */
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#define I2S_FIFO_TX_LEVEL_WORD_2 (2 << I2S_CTL_TXTH_Pos) /*!< TX threshold is 2 words \hideinitializer */
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#define I2S_FIFO_TX_LEVEL_WORD_3 (3 << I2S_CTL_TXTH_Pos) /*!< TX threshold is 3 words \hideinitializer */
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#define I2S_FIFO_TX_LEVEL_WORD_4 (4 << I2S_CTL_TXTH_Pos) /*!< TX threshold is 4 words \hideinitializer */
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#define I2S_FIFO_TX_LEVEL_WORD_5 (5 << I2S_CTL_TXTH_Pos) /*!< TX threshold is 5 words \hideinitializer */
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#define I2S_FIFO_TX_LEVEL_WORD_6 (6 << I2S_CTL_TXTH_Pos) /*!< TX threshold is 6 words \hideinitializer */
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#define I2S_FIFO_TX_LEVEL_WORD_7 (7 << I2S_CTL_TXTH_Pos) /*!< TX threshold is 7 words \hideinitializer */
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#define I2S_FIFO_RX_LEVEL_WORD_1 0 /*!< RX threshold is 1 word \hideinitializer */
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#define I2S_FIFO_RX_LEVEL_WORD_2 (1 << I2S_CTL_RXTH_Pos) /*!< RX threshold is 2 words \hideinitializer */
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#define I2S_FIFO_RX_LEVEL_WORD_3 (2 << I2S_CTL_RXTH_Pos) /*!< RX threshold is 3 words \hideinitializer */
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#define I2S_FIFO_RX_LEVEL_WORD_4 (3 << I2S_CTL_RXTH_Pos) /*!< RX threshold is 4 words \hideinitializer */
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#define I2S_FIFO_RX_LEVEL_WORD_5 (4 << I2S_CTL_RXTH_Pos) /*!< RX threshold is 5 words \hideinitializer */
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#define I2S_FIFO_RX_LEVEL_WORD_6 (5 << I2S_CTL_RXTH_Pos) /*!< RX threshold is 6 words \hideinitializer */
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#define I2S_FIFO_RX_LEVEL_WORD_7 (6 << I2S_CTL_RXTH_Pos) /*!< RX threshold is 7 words \hideinitializer */
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#define I2S_FIFO_RX_LEVEL_WORD_8 (7 << I2S_CTL_RXTH_Pos) /*!< RX threshold is 8 words \hideinitializer */
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/* I2S Record Channel */
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#define I2S_MONO_RIGHT 0 /*!< Record mono right channel \hideinitializer */
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#define I2S_MONO_LEFT I2S_CTL_RXLCH_Msk /*!< Record mono left channel \hideinitializer */
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/* I2S Channel */
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#define I2S_RIGHT 0 /*!< Select right channel \hideinitializer */
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#define I2S_LEFT 1 /*!< Select left channel \hideinitializer */
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/*@}*/ /* end of group NUC472_442_I2S_EXPORTED_CONSTANTS */
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/** @addtogroup NUC472_442_I2S_EXPORTED_FUNCTIONS I2S Exported Functions
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@{
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*/
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/*---------------------------------------------------------------------------------------------------------*/
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/* inline functions */
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/*---------------------------------------------------------------------------------------------------------*/
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/**
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* @brief Enable zero cross detect function.
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* @param[in] i2s is the base address of I2S module.
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* @param[in] u32ChMask is the mask for left or right channel. Valid values are:
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* - \ref I2S_RIGHT
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* - \ref I2S_LEFT
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* @return none
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* \hideinitializer
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*/
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static __INLINE void I2S_ENABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
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{
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if(u32ChMask == I2S_RIGHT)
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i2s->CTL |= I2S_CTL_RZCEN_Msk;
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else
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i2s->CTL |= I2S_CTL_LZCEN_Msk;
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}
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/**
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* @brief Disable zero cross detect function.
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* @param[in] i2s is the base address of I2S module.
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* @param[in] u32ChMask is the mask for left or right channel. Valid values are:
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* - \ref I2S_RIGHT
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* - \ref I2S_LEFT
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* @return none
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* \hideinitializer
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*/
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static __INLINE void I2S_DISABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
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{
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if(u32ChMask == I2S_RIGHT)
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i2s->CTL &= ~I2S_CTL_RZCEN_Msk;
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else
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i2s->CTL &= ~I2S_CTL_LZCEN_Msk;
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}
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/**
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* @brief Enable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO.
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* @param[in] i2s is the base address of I2S module.
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* @return none
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* \hideinitializer
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*/
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#define I2S_ENABLE_TXDMA(i2s) ( (i2s)->CTL |= I2S_CTL_TXPDMAEN_Msk )
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/**
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* @brief Disable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO.
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* @param[in] i2s is the base address of I2S module.
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* @return none
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* \hideinitializer
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*/
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#define I2S_DISABLE_TXDMA(i2s) ( (i2s)->CTL &= ~I2S_CTL_TXPDMAEN_Msk )
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/**
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* @brief Enable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO.
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* @param[in] i2s is the base address of I2S module.
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* @return none
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* \hideinitializer
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*/
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#define I2S_ENABLE_RXDMA(i2s) ( (i2s)->CTL |= I2S_CTL_RXPDMAEN_Msk )
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/**
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* @brief Disable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO.
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* @param[in] i2s is the base address of I2S module.
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* @return none
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* \hideinitializer
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*/
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#define I2S_DISABLE_RXDMA(i2s) ( (i2s)->CTL &= ~I2S_CTL_RXPDMAEN_Msk )
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/**
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* @brief Enable I2S Tx function .
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* @param[in] i2s is the base address of I2S module.
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* @return none
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* \hideinitializer
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*/
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#define I2S_ENABLE_TX(i2s) ( (i2s)->CTL |= I2S_CTL_TXEN_Msk )
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/**
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* @brief Disable I2S Tx function .
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* @param[in] i2s is the base address of I2S module.
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* @return none
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* \hideinitializer
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*/
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#define I2S_DISABLE_TX(i2s) ( (i2s)->CTL &= ~I2S_CTL_TXEN_Msk )
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/**
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* @brief Enable I2S Rx function .
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* @param[in] i2s is the base address of I2S module.
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* @return none
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* \hideinitializer
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*/
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#define I2S_ENABLE_RX(i2s) ( (i2s)->CTL |= I2S_CTL_RXEN_Msk )
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/**
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* @brief Disable I2S Rx function .
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* @param[in] i2s is the base address of I2S module.
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* @return none
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* \hideinitializer
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*/
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#define I2S_DISABLE_RX(i2s) ( (i2s)->CTL &= ~I2S_CTL_RXEN_Msk )
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/**
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* @brief Enable Tx Mute function .
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* @param[in] i2s is the base address of I2S module.
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* @return none
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* \hideinitializer
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*/
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#define I2S_ENABLE_TX_MUTE(i2s) ( (i2s)->CTL |= I2S_CTL_MUTE_Msk )
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/**
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* @brief Disable Tx Mute function .
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* @param[in] i2s is the base address of I2S module.
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* @return none
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* \hideinitializer
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*/
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#define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->CTL &= ~I2S_CTL_MUTE_Msk )
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/**
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* @brief Clear Tx FIFO. Internal pointer is reset to FIFO start point.
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* @param[in] i2s is the base address of I2S module.
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* @return none
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* \hideinitializer
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*/
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#define I2S_CLR_TX_FIFO(i2s) ( (i2s)->CTL |= I2S_CTL_TXCLR_Msk )
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/**
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* @brief Clear Rx FIFO. Internal pointer is reset to FIFO start point.
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* @param[in] i2s is the base address of I2S module.
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* @return none
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* \hideinitializer
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*/
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#define I2S_CLR_RX_FIFO(i2s) ( (i2s)->CTL |= I2S_CTL_RXCLR_Msk )
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/**
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* @brief This function sets the recording source channel when mono mode is used.
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* @param[in] i2s is the base address of I2S module.
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* @param[in] u32Ch left or right channel. Valid values are:
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* - \ref I2S_MONO_LEFT
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* - \ref I2S_MONO_RIGHT
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* @return none
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* \hideinitializer
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*/
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static __INLINE void I2S_SET_MONO_RX_CHANNEL(I2S_T *i2s, uint32_t u32Ch)
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{
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u32Ch == I2S_MONO_LEFT ?
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(i2s->CTL |= I2S_CTL_RXLCH_Msk) :
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(i2s->CTL &= ~I2S_CTL_RXLCH_Msk);
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}
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/**
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* @brief Write data to I2S Tx FIFO.
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* @param[in] i2s is the base address of I2S module.
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* @param[in] u32Data: The data written to FIFO.
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* @return none
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* \hideinitializer
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*/
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#define I2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TX = u32Data )
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/**
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* @brief Read Rx FIFO.
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* @param[in] i2s is the base address of I2S module.
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* @return Data in Rx FIFO.
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* \hideinitializer
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*/
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#define I2S_READ_RX_FIFO(i2s) ( (i2s)->RX )
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/**
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* @brief This function gets the interrupt flag according to the mask parameter.
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* @param[in] i2s is the base address of I2S module.
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* @param[in] u32Mask is the mask for the all interrupt flags.
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* @return The masked bit value of interrupt flag.
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* \hideinitializer
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*/
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#define I2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS & (u32Mask) )
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/**
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* @brief This function clears the interrupt flag according to the mask parameter.
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* @param[in] i2s is the base address of I2S module.
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* @param[in] u32Mask is the mask for the all interrupt flags.
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* @return none
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* \hideinitializer
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*/
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#define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS |= (u32Mask) )
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/**
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* @brief Get transmit FIFO level
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* @param[in] i2s is the base address of I2S module.
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* @return FIFO level
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* \hideinitializer
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*/
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#define I2S_GET_TX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS & I2S_STATUS_TXCNT_Msk) >> I2S_STATUS_TXCNT_Pos) & 0xF )
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/**
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* @brief Get receive FIFO level
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* @param[in] i2s is the base address of I2S module.
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* @return FIFO level
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* \hideinitializer
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*/
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#define I2S_GET_RX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS & I2S_STATUS_RXCNT_Msk) >> I2S_STATUS_RXCNT_Pos) & 0xF )
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uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat, uint32_t u32AudioInterface);
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void I2S_Close(I2S_T *i2s);
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void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask);
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void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask);
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uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock);
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void I2S_DisableMCLK(I2S_T *i2s);
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void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
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/*@}*/ /* end of group NUC472_442_I2S_EXPORTED_FUNCTIONS */
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/*@}*/ /* end of group NUC472_442_I2S_Driver */
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/*@}*/ /* end of group NUC472_442_Device_Driver */
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#ifdef __cplusplus
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}
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#endif
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#endif
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/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
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