2020-10-14 15:02:23 +08:00
|
|
|
/*
|
2021-03-14 15:33:55 +08:00
|
|
|
* Copyright (c) 2006-2021, RT-Thread Development Team
|
2020-10-14 15:02:23 +08:00
|
|
|
*
|
|
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
|
|
*
|
|
|
|
* Change Logs:
|
|
|
|
* Date Author Notes
|
|
|
|
* 2018-11-06 SummerGift first version
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include "board.h"
|
|
|
|
|
|
|
|
void SystemClock_Config(void)
|
|
|
|
{
|
|
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
|
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
|
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
|
|
|
|
|
|
|
/** Configure LSE Drive Capability
|
|
|
|
*/
|
|
|
|
HAL_PWR_EnableBkUpAccess();
|
|
|
|
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
|
|
|
|
/** Configure the main internal regulator output voltage
|
|
|
|
*/
|
|
|
|
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
|
|
|
|
/** Initializes the RCC Oscillators according to the specified parameters
|
|
|
|
* in the RCC_OscInitTypeDef structure.
|
|
|
|
*/
|
|
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSI1
|
|
|
|
|RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE
|
|
|
|
|RCC_OSCILLATORTYPE_MSI;
|
|
|
|
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
|
|
|
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
|
|
|
|
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
|
|
|
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
|
|
|
|
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
|
|
|
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
|
|
|
|
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
|
|
|
|
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
|
|
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
|
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
|
|
|
|
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
|
|
|
|
RCC_OscInitStruct.PLL.PLLN = 32;
|
|
|
|
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
|
|
|
|
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
|
|
|
|
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
|
|
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
|
|
|
{
|
|
|
|
Error_Handler();
|
|
|
|
}
|
|
|
|
/** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers
|
|
|
|
*/
|
|
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
|
|
|
|
|RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
|
|
|
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
|
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
|
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
|
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
|
|
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
|
|
|
RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
|
|
|
|
RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
|
|
|
|
|
|
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
|
|
|
|
{
|
|
|
|
Error_Handler();
|
|
|
|
}
|
|
|
|
/** Initializes the peripherals clocks
|
|
|
|
*/
|
|
|
|
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS|RCC_PERIPHCLK_RTC
|
|
|
|
|RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_LPUART1
|
|
|
|
|RCC_PERIPHCLK_USB|RCC_PERIPHCLK_ADC;
|
|
|
|
PeriphClkInitStruct.PLLSAI1.PLLN = 24;
|
|
|
|
PeriphClkInitStruct.PLLSAI1.PLLP = RCC_PLLP_DIV2;
|
|
|
|
PeriphClkInitStruct.PLLSAI1.PLLQ = RCC_PLLQ_DIV2;
|
|
|
|
PeriphClkInitStruct.PLLSAI1.PLLR = RCC_PLLR_DIV2;
|
|
|
|
PeriphClkInitStruct.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_USBCLK|RCC_PLLSAI1_ADCCLK;
|
|
|
|
PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
|
|
|
|
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
|
|
|
|
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
|
|
|
|
PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI1;
|
|
|
|
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
|
|
|
|
PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSI;
|
|
|
|
PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
|
|
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
|
|
|
{
|
|
|
|
Error_Handler();
|
|
|
|
}
|
|
|
|
/* USER CODE BEGIN Smps */
|
|
|
|
|
|
|
|
/* USER CODE END Smps */
|
|
|
|
/** Enable MSI Auto calibration
|
|
|
|
*/
|
|
|
|
HAL_RCCEx_EnableMSIPLLMode();
|
|
|
|
}
|