2021-05-12 19:15:17 +08:00
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/**************************************************************************//**
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* @file sdh.c
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* @brief N9H30 SDH driver source file
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*
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* @note
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* SPDX-License-Identifier: Apache-2.0
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* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "N9H30.h"
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#include "nu_sys.h"
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#include "nu_sdh.h"
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/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
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@{
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*/
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/** @addtogroup N9H30_SDH_Driver SDH Driver
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@{
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*/
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/** @addtogroup N9H30_SDH_EXPORTED_FUNCTIONS SDH Exported Functions
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@{
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*/
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#define SDH_BLOCK_SIZE 512ul
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/** @cond HIDDEN_SYMBOLS */
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/* global variables */
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/* For response R3 (such as ACMD41, CRC-7 is invalid; but SD controller will still */
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/* calculate CRC-7 and get an error result, software should ignore this error and clear SDISR [CRC_IF] flag */
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/* _sd_uR3_CMD is the flag for it. 1 means software should ignore CRC-7 error */
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#ifdef __ICCARM__
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#pragma data_alignment = 32
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static uint8_t _SDH0_ucSDHCBuffer[512];
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static uint8_t _SDH1_ucSDHCBuffer[512];
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#else
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static uint8_t _SDH0_ucSDHCBuffer[512] __attribute__((aligned(32)));
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static uint8_t _SDH1_ucSDHCBuffer[512] __attribute__((aligned(32)));
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#endif
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void SDH_CheckRB(SDH_T *sdh)
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{
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while (1)
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{
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sdh->CTL |= SDH_CTL_CLK8OEN_Msk;
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while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk)
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{
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}
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if ((sdh->INTSTS & SDH_INTSTS_DAT0STS_Msk) == SDH_INTSTS_DAT0STS_Msk)
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{
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break;
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}
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}
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}
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2021-06-16 16:53:41 +08:00
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uint32_t SDH_SDCommand(SDH_T *sdh, SDH_INFO_T *pSD, uint32_t ucCmd, uint32_t uArg)
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2021-05-12 19:15:17 +08:00
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{
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volatile uint32_t buf, val = 0ul;
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sdh->CMDARG = uArg;
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buf = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | (ucCmd << 8ul) | (SDH_CTL_COEN_Msk);
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sdh->CTL = buf;
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while ((sdh->CTL & SDH_CTL_COEN_Msk) == SDH_CTL_COEN_Msk)
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{
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if (pSD->IsCardInsert == 0ul)
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{
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val = SDH_NO_SD_CARD;
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}
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}
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return val;
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}
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2021-06-16 16:53:41 +08:00
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uint32_t SDH_SDCmdAndRsp(SDH_T *sdh, SDH_INFO_T *pSD, uint32_t ucCmd, uint32_t uArg, uint32_t ntickCount)
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2021-05-12 19:15:17 +08:00
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{
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volatile uint32_t buf;
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sdh->CMDARG = uArg;
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buf = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | (ucCmd << 8ul) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk);
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sdh->CTL = buf;
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if (ntickCount > 0ul)
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{
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while ((sdh->CTL & SDH_CTL_RIEN_Msk) == SDH_CTL_RIEN_Msk)
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{
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if (ntickCount-- == 0ul)
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{
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sdh->CTL |= SDH_CTL_CTLRST_Msk; /* reset SD engine */
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return 2ul;
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}
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if (pSD->IsCardInsert == FALSE)
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{
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return SDH_NO_SD_CARD;
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}
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}
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}
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else
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{
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while ((sdh->CTL & SDH_CTL_RIEN_Msk) == SDH_CTL_RIEN_Msk)
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{
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if (pSD->IsCardInsert == FALSE)
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{
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return SDH_NO_SD_CARD;
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}
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}
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}
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if (pSD->R7Flag)
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{
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uint32_t tmp0 = 0ul, tmp1 = 0ul;
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tmp1 = sdh->RESP1 & 0xfful;
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tmp0 = sdh->RESP0 & 0xful;
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if ((tmp1 != 0x55ul) && (tmp0 != 0x01ul))
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{
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pSD->R7Flag = 0ul;
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return SDH_CMD8_ERROR;
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}
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}
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if (!pSD->R3Flag)
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{
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if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) == SDH_INTSTS_CRC7_Msk) /* check CRC7 */
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{
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return Successful;
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}
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else
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{
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return SDH_CRC7_ERROR;
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}
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}
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else
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{
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/* ignore CRC error for R3 case */
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pSD->R3Flag = 0ul;
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sdh->INTSTS = SDH_INTSTS_CRCIF_Msk;
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return Successful;
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}
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}
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uint32_t SDH_Swap32(uint32_t val)
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{
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uint32_t buf;
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buf = val;
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val <<= 24;
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val |= (buf << 8) & 0xff0000ul;
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val |= (buf >> 8) & 0xff00ul;
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val |= (buf >> 24) & 0xfful;
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return val;
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}
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/* Get 16 bytes CID or CSD */
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2021-06-16 16:53:41 +08:00
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uint32_t SDH_SDCmdAndRsp2(SDH_T *sdh, SDH_INFO_T *pSD, uint32_t ucCmd, uint32_t uArg, uint32_t puR2ptr[])
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2021-05-12 19:15:17 +08:00
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{
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uint32_t i, buf;
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uint32_t tmpBuf[5];
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sdh->CMDARG = uArg;
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buf = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | (ucCmd << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_R2EN_Msk);
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sdh->CTL = buf;
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while ((sdh->CTL & SDH_CTL_R2EN_Msk) == SDH_CTL_R2EN_Msk)
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{
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if (pSD->IsCardInsert == FALSE)
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{
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return SDH_NO_SD_CARD;
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}
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}
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if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) == SDH_INTSTS_CRC7_Msk)
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{
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for (i = 0ul; i < 5ul; i++)
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{
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tmpBuf[i] = SDH_Swap32(sdh->FB[i]);
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}
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for (i = 0ul; i < 4ul; i++)
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{
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puR2ptr[i] = ((tmpBuf[i] & 0x00fffffful) << 8) | ((tmpBuf[i + 1ul] & 0xff000000ul) >> 24);
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}
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}
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else
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{
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return SDH_CRC7_ERROR;
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}
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return Successful;
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}
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2021-06-16 16:53:41 +08:00
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uint32_t SDH_SDCmdAndRspDataIn(SDH_T *sdh, SDH_INFO_T *pSD, uint32_t ucCmd, uint32_t uArg)
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2021-05-12 19:15:17 +08:00
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{
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volatile uint32_t buf;
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sdh->CMDARG = uArg;
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buf = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | (ucCmd << 8ul) |
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(SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk);
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sdh->CTL = buf;
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while ((sdh->CTL & SDH_CTL_RIEN_Msk) == SDH_CTL_RIEN_Msk)
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{
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if (pSD->IsCardInsert == FALSE)
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{
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return SDH_NO_SD_CARD;
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}
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}
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while ((sdh->CTL & SDH_CTL_DIEN_Msk) == SDH_CTL_DIEN_Msk)
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{
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if (pSD->IsCardInsert == FALSE)
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{
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return SDH_NO_SD_CARD;
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}
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}
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if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) != SDH_INTSTS_CRC7_Msk)
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{
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/* check CRC7 */
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return SDH_CRC7_ERROR;
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}
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if ((sdh->INTSTS & SDH_INTSTS_CRC16_Msk) != SDH_INTSTS_CRC16_Msk)
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{
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/* check CRC16 */
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return SDH_CRC16_ERROR;
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}
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return 0ul;
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}
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/* there are 8 bits for divider0, maximum is 256 */
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#define SDH_CLK_DIV0_MAX 256ul
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2021-06-16 16:53:41 +08:00
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2021-05-12 19:15:17 +08:00
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void SDH_Set_clock(SDH_T *sdh, uint32_t sd_clock_khz)
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{
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UINT32 div;
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2021-06-16 16:53:41 +08:00
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UINT32 reg;
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2021-05-12 19:15:17 +08:00
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uint32_t SDH_ReferenceClock;
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2021-06-16 16:53:41 +08:00
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if (sdh == SDH0)
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reg = REG_CLK_DIVCTL3;
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2021-05-12 19:15:17 +08:00
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else
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2021-06-16 16:53:41 +08:00
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reg = REG_CLK_DIVCTL9;
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2021-05-12 19:15:17 +08:00
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2021-06-21 22:04:34 +08:00
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if (sd_clock_khz <= 2000)
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2021-05-12 19:15:17 +08:00
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{
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2021-06-21 22:04:34 +08:00
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SDH_ReferenceClock = 12000;
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2021-06-16 16:53:41 +08:00
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outpw(reg, (inpw(reg) & ~0x18) | (0x0 << 3)); // SD clock from XIN [4:3]
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2021-06-21 22:04:34 +08:00
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}
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else
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{
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2021-06-16 16:53:41 +08:00
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SDH_ReferenceClock = 300000;
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outpw(reg, (inpw(reg) & ~0x18) | (0x3 << 3)); // SD clock from UPLL [4:3]
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2021-05-12 19:15:17 +08:00
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}
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2021-06-21 22:04:34 +08:00
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div = (SDH_ReferenceClock / sd_clock_khz) - 1;
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if (div >= SDH_CLK_DIV0_MAX) div = 0xff;
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2021-06-16 16:53:41 +08:00
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outpw(reg, (inpw(reg) & ~0xff00) | ((div) << 8)); // SD clock divided by CLKDIV3[SD_N] [15:8]
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2021-05-12 19:15:17 +08:00
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}
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2021-06-16 16:53:41 +08:00
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uint32_t SDH_CardDetection(SDH_T *sdh, SDH_INFO_T *pSD, uint32_t card_num)
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2021-05-12 19:15:17 +08:00
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{
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uint32_t i, val = TRUE;
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2021-06-16 16:53:41 +08:00
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uint32_t u32INTEN_CDSRC_Msk;
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uint32_t u32INTSTS_CDSTS_Msk;
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uint32_t u32CTL_CLKKEEP_Msk;
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2021-05-12 19:15:17 +08:00
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2021-06-29 00:37:32 +08:00
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if (card_num & SD_PORT0)
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{
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u32INTEN_CDSRC_Msk = SDH_INTEN_CDSRC_Msk;
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u32INTSTS_CDSTS_Msk = SDH_INTSTS_CDSTS_Msk;
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u32CTL_CLKKEEP_Msk = SDH_CTL_CLKKEEP0_Msk;
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}
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else if (card_num & SD_PORT1)
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2021-05-12 19:15:17 +08:00
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{
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2021-06-16 16:53:41 +08:00
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u32INTEN_CDSRC_Msk = SDH_INTEN_CDSRC1_Msk;
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u32INTSTS_CDSTS_Msk = SDH_INTSTS_CDSTS1_Msk;
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u32CTL_CLKKEEP_Msk = SDH_CTL_CLKKEEP1_Msk;
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2021-05-12 19:15:17 +08:00
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}
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2021-12-17 17:20:33 +08:00
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else
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{
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return FALSE;
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}
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2021-06-21 22:04:34 +08:00
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2021-06-16 16:53:41 +08:00
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if ((sdh->INTEN & u32INTEN_CDSRC_Msk) == u32INTEN_CDSRC_Msk) /* Card detect pin from GPIO */
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2021-05-12 19:15:17 +08:00
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{
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2021-06-16 16:53:41 +08:00
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if ((sdh->INTSTS & u32INTSTS_CDSTS_Msk) == u32INTSTS_CDSTS_Msk) /* Card remove */
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2021-05-12 19:15:17 +08:00
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{
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pSD->IsCardInsert = (uint8_t)FALSE;
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val = FALSE;
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}
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else
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{
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pSD->IsCardInsert = (uint8_t)TRUE;
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}
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2021-06-16 16:53:41 +08:00
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2021-05-12 19:15:17 +08:00
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}
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2021-06-16 16:53:41 +08:00
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else if ((sdh->INTEN & u32INTEN_CDSRC_Msk) != u32INTEN_CDSRC_Msk)
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2021-05-12 19:15:17 +08:00
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{
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2021-06-16 16:53:41 +08:00
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sdh->CTL |= u32CTL_CLKKEEP_Msk;
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2021-05-12 19:15:17 +08:00
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for (i = 0ul; i < 5000ul; i++)
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{
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}
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2021-06-16 16:53:41 +08:00
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if ((sdh->INTSTS & u32INTSTS_CDSTS_Msk) == u32INTSTS_CDSTS_Msk) /* Card insert */
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2021-05-12 19:15:17 +08:00
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{
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pSD->IsCardInsert = (uint8_t)TRUE;
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}
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else
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{
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pSD->IsCardInsert = (uint8_t)FALSE;
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val = FALSE;
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}
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2021-06-16 16:53:41 +08:00
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sdh->CTL &= ~u32CTL_CLKKEEP_Msk;
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2021-05-12 19:15:17 +08:00
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}
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return val;
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}
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2021-06-29 00:37:32 +08:00
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uint32_t SDH_WhichCardIsSelected(SDH_T *sdh)
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|
{
|
|
|
|
return (sdh->CTL & SDH_CTL_SDPORT_Msk) ? SD_PORT1 : SD_PORT0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void SDH_CardSelect(SDH_T *sdh, SDH_INFO_T *pSD, uint32_t u32CardSrc)
|
2021-06-21 22:04:34 +08:00
|
|
|
{
|
|
|
|
if (u32CardSrc & SD_PORT0)
|
|
|
|
{
|
|
|
|
sdh->CTL &= ~SDH_CTL_SDPORT_Msk;
|
|
|
|
}
|
|
|
|
else if (u32CardSrc & SD_PORT1)
|
|
|
|
{
|
|
|
|
sdh->CTL &= ~SDH_CTL_SDPORT_Msk;
|
|
|
|
sdh->CTL |= (1 << SDH_CTL_SDPORT_Pos);
|
|
|
|
}
|
2021-06-29 00:37:32 +08:00
|
|
|
|
|
|
|
switch (pSD->CardType)
|
|
|
|
{
|
|
|
|
case SDH_TYPE_MMC:
|
|
|
|
sdh->CTL |= SDH_CTL_DBW_Msk; /* set bus width to 4-bit mode for SD host controller */
|
|
|
|
SDH_Set_clock(sdh, MMC_FREQ);
|
|
|
|
break;
|
|
|
|
case SDH_TYPE_SD_LOW:
|
|
|
|
case SDH_TYPE_EMMC:
|
|
|
|
sdh->CTL |= SDH_CTL_DBW_Msk; /* set bus width to 4-bit mode for SD host controller */
|
|
|
|
SDH_Set_clock(sdh, SD_FREQ);
|
|
|
|
break;
|
|
|
|
case SDH_TYPE_SD_HIGH:
|
|
|
|
sdh->CTL |= SDH_CTL_DBW_Msk; /* set bus width to 4-bit mode for SD host controller */
|
|
|
|
SDH_Set_clock(sdh, SDHC_FREQ);
|
|
|
|
break;
|
|
|
|
case SDH_TYPE_UNKNOWN:
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
2021-06-21 22:04:34 +08:00
|
|
|
}
|
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
uint32_t SDH_Init(SDH_T *sdh, SDH_INFO_T *pSD)
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
|
|
|
uint32_t volatile i, status;
|
|
|
|
uint32_t resp;
|
|
|
|
uint32_t CIDBuffer[4];
|
|
|
|
uint32_t volatile u32CmdTimeOut;
|
|
|
|
|
|
|
|
/* set the clock to 300KHz */
|
|
|
|
SDH_Set_clock(sdh, 300ul);
|
|
|
|
|
|
|
|
/* power ON 74 clock */
|
|
|
|
sdh->CTL |= SDH_CTL_CLK74OEN_Msk;
|
|
|
|
|
|
|
|
while ((sdh->CTL & SDH_CTL_CLK74OEN_Msk) == SDH_CTL_CLK74OEN_Msk)
|
|
|
|
{
|
|
|
|
if (pSD->IsCardInsert == FALSE)
|
|
|
|
{
|
|
|
|
return SDH_NO_SD_CARD;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
SDH_SDCommand(sdh, pSD, 0ul, 0ul); /* reset all cards */
|
2021-05-12 19:15:17 +08:00
|
|
|
for (i = 0x1000ul; i > 0ul; i--)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
/* initial SDHC */
|
|
|
|
pSD->R7Flag = 1ul;
|
|
|
|
u32CmdTimeOut = 0xFFFFFul;
|
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
i = SDH_SDCmdAndRsp(sdh, pSD, 8ul, 0x00000155ul, u32CmdTimeOut);
|
2021-05-12 19:15:17 +08:00
|
|
|
if (i == Successful)
|
|
|
|
{
|
|
|
|
/* SD 2.0 */
|
2021-06-16 16:53:41 +08:00
|
|
|
SDH_SDCmdAndRsp(sdh, pSD, 55ul, 0x00ul, u32CmdTimeOut);
|
2021-05-12 19:15:17 +08:00
|
|
|
pSD->R3Flag = 1ul;
|
2021-06-16 16:53:41 +08:00
|
|
|
SDH_SDCmdAndRsp(sdh, pSD, 41ul, 0x40ff8000ul, u32CmdTimeOut); /* 2.7v-3.6v */
|
2021-05-12 19:15:17 +08:00
|
|
|
resp = sdh->RESP0;
|
|
|
|
|
|
|
|
while ((resp & 0x00800000ul) != 0x00800000ul) /* check if card is ready */
|
|
|
|
{
|
2021-06-16 16:53:41 +08:00
|
|
|
SDH_SDCmdAndRsp(sdh, pSD, 55ul, 0x00ul, u32CmdTimeOut);
|
2021-05-12 19:15:17 +08:00
|
|
|
pSD->R3Flag = 1ul;
|
2021-06-16 16:53:41 +08:00
|
|
|
SDH_SDCmdAndRsp(sdh, pSD, 41ul, 0x40ff8000ul, u32CmdTimeOut); /* 3.0v-3.4v */
|
2021-05-12 19:15:17 +08:00
|
|
|
resp = sdh->RESP0;
|
|
|
|
}
|
|
|
|
if ((resp & 0x00400000ul) == 0x00400000ul)
|
|
|
|
{
|
|
|
|
pSD->CardType = SDH_TYPE_SD_HIGH;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
pSD->CardType = SDH_TYPE_SD_LOW;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* SD 1.1 */
|
2021-06-16 16:53:41 +08:00
|
|
|
SDH_SDCommand(sdh, pSD, 0ul, 0ul); /* reset all cards */
|
2021-05-12 19:15:17 +08:00
|
|
|
for (i = 0x100ul; i > 0ul; i--)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
i = SDH_SDCmdAndRsp(sdh, pSD, 55ul, 0x00ul, u32CmdTimeOut);
|
2021-05-12 19:15:17 +08:00
|
|
|
if (i == 2ul) /* MMC memory */
|
|
|
|
{
|
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
SDH_SDCommand(sdh, pSD, 0ul, 0ul); /* reset */
|
2021-05-12 19:15:17 +08:00
|
|
|
for (i = 0x100ul; i > 0ul; i--)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
pSD->R3Flag = 1ul;
|
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
if (SDH_SDCmdAndRsp(sdh, pSD, 1ul, 0x40ff8000ul, u32CmdTimeOut) != 2ul) /* eMMC memory */
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
|
|
|
resp = sdh->RESP0;
|
|
|
|
while ((resp & 0x00800000ul) != 0x00800000ul)
|
|
|
|
{
|
|
|
|
/* check if card is ready */
|
|
|
|
pSD->R3Flag = 1ul;
|
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
SDH_SDCmdAndRsp(sdh, pSD, 1ul, 0x40ff8000ul, u32CmdTimeOut); /* high voltage */
|
2021-05-12 19:15:17 +08:00
|
|
|
resp = sdh->RESP0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((resp & 0x00400000ul) == 0x00400000ul)
|
|
|
|
{
|
|
|
|
pSD->CardType = SDH_TYPE_EMMC;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
pSD->CardType = SDH_TYPE_MMC;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
pSD->CardType = SDH_TYPE_UNKNOWN;
|
|
|
|
return SDH_ERR_DEVICE;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else if (i == 0ul) /* SD Memory */
|
|
|
|
{
|
|
|
|
pSD->R3Flag = 1ul;
|
2021-06-16 16:53:41 +08:00
|
|
|
SDH_SDCmdAndRsp(sdh, pSD, 41ul, 0x00ff8000ul, u32CmdTimeOut); /* 3.0v-3.4v */
|
2021-05-12 19:15:17 +08:00
|
|
|
resp = sdh->RESP0;
|
|
|
|
while ((resp & 0x00800000ul) != 0x00800000ul) /* check if card is ready */
|
|
|
|
{
|
2021-06-16 16:53:41 +08:00
|
|
|
SDH_SDCmdAndRsp(sdh, pSD, 55ul, 0x00ul, u32CmdTimeOut);
|
2021-05-12 19:15:17 +08:00
|
|
|
pSD->R3Flag = 1ul;
|
2021-06-16 16:53:41 +08:00
|
|
|
SDH_SDCmdAndRsp(sdh, pSD, 41ul, 0x00ff8000ul, u32CmdTimeOut); /* 3.0v-3.4v */
|
2021-05-12 19:15:17 +08:00
|
|
|
resp = sdh->RESP0;
|
|
|
|
}
|
|
|
|
pSD->CardType = SDH_TYPE_SD_LOW;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
pSD->CardType = SDH_TYPE_UNKNOWN;
|
2021-06-29 00:37:32 +08:00
|
|
|
|
2021-05-12 19:15:17 +08:00
|
|
|
return SDH_INIT_ERROR;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (pSD->CardType != SDH_TYPE_UNKNOWN)
|
|
|
|
{
|
2021-06-16 16:53:41 +08:00
|
|
|
SDH_SDCmdAndRsp2(sdh, pSD, 2ul, 0x00ul, CIDBuffer);
|
2021-05-12 19:15:17 +08:00
|
|
|
if ((pSD->CardType == SDH_TYPE_MMC) || (pSD->CardType == SDH_TYPE_EMMC))
|
|
|
|
{
|
2021-06-16 16:53:41 +08:00
|
|
|
if ((status = SDH_SDCmdAndRsp(sdh, pSD, 3ul, 0x10000ul, 0ul)) != Successful) /* set RCA */
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
pSD->RCA = 0x10000ul;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2021-06-16 16:53:41 +08:00
|
|
|
if ((status = SDH_SDCmdAndRsp(sdh, pSD, 3ul, 0x00ul, 0ul)) != Successful) /* get RCA */
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
pSD->RCA = (sdh->RESP0 << 8) & 0xffff0000;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return Successful;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
uint32_t SDH_SwitchToHighSpeed(SDH_T *sdh, SDH_INFO_T *pSD)
|
|
|
|
{
|
|
|
|
uint32_t volatile status = 0ul;
|
|
|
|
uint16_t current_comsumption, busy_status0;
|
|
|
|
|
|
|
|
sdh->DMASA = (uint32_t)pSD->dmabuf;
|
|
|
|
sdh->BLEN = 63ul;
|
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
if ((status = SDH_SDCmdAndRspDataIn(sdh, pSD, 6ul, 0x00ffff01ul)) != Successful)
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
|
|
|
return Fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
current_comsumption = (uint16_t)(*pSD->dmabuf) << 8;
|
|
|
|
current_comsumption |= (uint16_t)(*(pSD->dmabuf + 1));
|
|
|
|
if (!current_comsumption)
|
|
|
|
{
|
|
|
|
return Fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
busy_status0 = (uint16_t)(*(pSD->dmabuf + 28)) << 8;
|
|
|
|
busy_status0 |= (uint16_t)(*(pSD->dmabuf + 29));
|
|
|
|
|
|
|
|
if (!busy_status0) /* function ready */
|
|
|
|
{
|
|
|
|
sdh->DMASA = (uint32_t)pSD->dmabuf;
|
|
|
|
sdh->BLEN = 63ul; /* 512 bit */
|
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
if ((status = SDH_SDCmdAndRspDataIn(sdh, pSD, 6ul, 0x80ffff01ul)) != Successful)
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
|
|
|
return Fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* function change timing: 8 clocks */
|
|
|
|
sdh->CTL |= SDH_CTL_CLK8OEN_Msk;
|
|
|
|
while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
current_comsumption = (uint16_t)(*pSD->dmabuf) << 8;
|
|
|
|
current_comsumption |= (uint16_t)(*(pSD->dmabuf + 1));
|
|
|
|
if (!current_comsumption)
|
|
|
|
{
|
|
|
|
return Fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
return Successful;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
return Fail;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
uint32_t SDH_SelectCardType(SDH_T *sdh, SDH_INFO_T *pSD)
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
|
|
|
uint32_t volatile status = 0ul;
|
|
|
|
uint32_t param;
|
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
if ((status = SDH_SDCmdAndRsp(sdh, pSD, 7ul, pSD->RCA, 0ul)) != Successful)
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
|
|
|
SDH_CheckRB(sdh);
|
|
|
|
|
|
|
|
/* if SD card set 4bit */
|
|
|
|
if (pSD->CardType == SDH_TYPE_SD_HIGH)
|
|
|
|
{
|
|
|
|
sdh->DMASA = (uint32_t)pSD->dmabuf;
|
|
|
|
sdh->BLEN = 0x07ul; /* 64 bit */
|
|
|
|
sdh->DMACTL |= SDH_DMACTL_DMARST_Msk;
|
|
|
|
while ((sdh->DMACTL & SDH_DMACTL_DMARST_Msk) == 0x2);
|
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
if ((status = SDH_SDCmdAndRsp(sdh, pSD, 55ul, pSD->RCA, 0ul)) != Successful)
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
|
|
|
return status;
|
|
|
|
}
|
2021-06-16 16:53:41 +08:00
|
|
|
if ((status = SDH_SDCmdAndRspDataIn(sdh, pSD, 51ul, 0x00ul)) != Successful)
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((*pSD->dmabuf & 0xful) == 0x2ul)
|
|
|
|
{
|
|
|
|
status = SDH_SwitchToHighSpeed(sdh, pSD);
|
|
|
|
if (status == Successful)
|
|
|
|
{
|
|
|
|
/* divider */
|
|
|
|
SDH_Set_clock(sdh, SDHC_FREQ);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
if ((status = SDH_SDCmdAndRsp(sdh, pSD, 55ul, pSD->RCA, 0ul)) != Successful)
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
|
|
|
return status;
|
|
|
|
}
|
2021-06-16 16:53:41 +08:00
|
|
|
if ((status = SDH_SDCmdAndRsp(sdh, pSD, 6ul, 0x02ul, 0ul)) != Successful) /* set bus width */
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
|
|
|
sdh->CTL |= SDH_CTL_DBW_Msk;
|
|
|
|
}
|
|
|
|
else if (pSD->CardType == SDH_TYPE_SD_LOW)
|
|
|
|
{
|
|
|
|
sdh->DMASA = (uint32_t)pSD->dmabuf;;
|
|
|
|
sdh->BLEN = 0x07ul;
|
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
if ((status = SDH_SDCmdAndRsp(sdh, pSD, 55ul, pSD->RCA, 0ul)) != Successful)
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
|
|
|
return status;
|
|
|
|
}
|
2021-06-16 16:53:41 +08:00
|
|
|
if ((status = SDH_SDCmdAndRspDataIn(sdh, pSD, 51ul, 0x00ul)) != Successful)
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* set data bus width. ACMD6 for SD card, SDCR_DBW for host. */
|
2021-06-16 16:53:41 +08:00
|
|
|
if ((status = SDH_SDCmdAndRsp(sdh, pSD, 55ul, pSD->RCA, 0ul)) != Successful)
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
if ((status = SDH_SDCmdAndRsp(sdh, pSD, 6ul, 0x02ul, 0ul)) != Successful)
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
|
|
|
sdh->CTL |= SDH_CTL_DBW_Msk;
|
|
|
|
}
|
|
|
|
else if ((pSD->CardType == SDH_TYPE_MMC) || (pSD->CardType == SDH_TYPE_EMMC))
|
|
|
|
{
|
|
|
|
|
|
|
|
if (pSD->CardType == SDH_TYPE_MMC)
|
|
|
|
{
|
|
|
|
sdh->CTL &= ~SDH_CTL_DBW_Msk;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*--- sent CMD6 to MMC card to set bus width to 4 bits mode */
|
|
|
|
/* set CMD6 argument Access field to 3, Index to 183, Value to 1 (4-bit mode) */
|
|
|
|
param = (3ul << 24) | (183ul << 16) | (1ul << 8);
|
2021-06-16 16:53:41 +08:00
|
|
|
if ((status = SDH_SDCmdAndRsp(sdh, pSD, 6ul, param, 0ul)) != Successful)
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
SDH_CheckRB(sdh);
|
|
|
|
|
|
|
|
sdh->CTL |= SDH_CTL_DBW_Msk; /* set bus width to 4-bit mode for SD host controller */
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
if ((status = SDH_SDCmdAndRsp(sdh, pSD, 16ul, SDH_BLOCK_SIZE, 0ul)) != Successful)
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
sdh->BLEN = SDH_BLOCK_SIZE - 1ul;
|
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
SDH_SDCommand(sdh, pSD, 7ul, 0ul);
|
2021-05-12 19:15:17 +08:00
|
|
|
sdh->CTL |= SDH_CTL_CLK8OEN_Msk;
|
|
|
|
while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
sdh->INTEN |= SDH_INTEN_BLKDIEN_Msk;
|
|
|
|
|
|
|
|
return Successful;
|
|
|
|
}
|
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
void SDH_Get_SD_info(SDH_T *sdh, SDH_INFO_T *pSD)
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
|
|
|
unsigned int R_LEN, C_Size, MULT, size;
|
|
|
|
uint32_t Buffer[4];
|
|
|
|
//unsigned char *ptr;
|
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
SDH_SDCmdAndRsp2(sdh, pSD, 9ul, pSD->RCA, Buffer);
|
2021-05-12 19:15:17 +08:00
|
|
|
|
|
|
|
if ((pSD->CardType == SDH_TYPE_MMC) || (pSD->CardType == SDH_TYPE_EMMC))
|
|
|
|
{
|
|
|
|
/* for MMC/eMMC card */
|
|
|
|
if ((Buffer[0] & 0xc0000000) == 0xc0000000)
|
|
|
|
{
|
|
|
|
/* CSD_STRUCTURE [127:126] is 3 */
|
|
|
|
/* CSD version depend on EXT_CSD register in eMMC v4.4 for card size > 2GB */
|
2021-06-16 16:53:41 +08:00
|
|
|
SDH_SDCmdAndRsp(sdh, pSD, 7ul, pSD->RCA, 0ul);
|
2021-05-12 19:15:17 +08:00
|
|
|
|
|
|
|
//ptr = (uint8_t *)((uint32_t)_SDH_ucSDHCBuffer );
|
|
|
|
sdh->DMASA = (uint32_t)pSD->dmabuf;;
|
|
|
|
sdh->BLEN = 511ul; /* read 512 bytes for EXT_CSD */
|
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
if (SDH_SDCmdAndRspDataIn(sdh, pSD, 8ul, 0x00ul) == Successful)
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
2021-06-16 16:53:41 +08:00
|
|
|
SDH_SDCommand(sdh, pSD, 7ul, 0ul);
|
2021-05-12 19:15:17 +08:00
|
|
|
sdh->CTL |= SDH_CTL_CLK8OEN_Msk;
|
|
|
|
while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
pSD->totalSectorN = (uint32_t)(*(pSD->dmabuf + 215)) << 24;
|
|
|
|
pSD->totalSectorN |= (uint32_t)(*(pSD->dmabuf + 214)) << 16;
|
|
|
|
pSD->totalSectorN |= (uint32_t)(*(pSD->dmabuf + 213)) << 8;
|
|
|
|
pSD->totalSectorN |= (uint32_t)(*(pSD->dmabuf + 212));
|
|
|
|
pSD->diskSize = pSD->totalSectorN / 2ul;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* CSD version v1.0/1.1/1.2 in eMMC v4.4 spec for card size <= 2GB */
|
|
|
|
R_LEN = (Buffer[1] & 0x000f0000ul) >> 16;
|
|
|
|
C_Size = ((Buffer[1] & 0x000003fful) << 2) | ((Buffer[2] & 0xc0000000ul) >> 30);
|
|
|
|
MULT = (Buffer[2] & 0x00038000ul) >> 15;
|
|
|
|
size = (C_Size + 1ul) * (1ul << (MULT + 2ul)) * (1ul << R_LEN);
|
|
|
|
|
|
|
|
pSD->diskSize = size / 1024ul;
|
|
|
|
pSD->totalSectorN = size / 512ul;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if ((Buffer[0] & 0xc0000000) != 0x0ul)
|
|
|
|
{
|
|
|
|
C_Size = ((Buffer[1] & 0x0000003ful) << 16) | ((Buffer[2] & 0xffff0000ul) >> 16);
|
|
|
|
size = (C_Size + 1ul) * 512ul; /* Kbytes */
|
|
|
|
|
|
|
|
pSD->diskSize = size;
|
|
|
|
pSD->totalSectorN = size << 1;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
R_LEN = (Buffer[1] & 0x000f0000ul) >> 16;
|
|
|
|
C_Size = ((Buffer[1] & 0x000003fful) << 2) | ((Buffer[2] & 0xc0000000ul) >> 30);
|
|
|
|
MULT = (Buffer[2] & 0x00038000ul) >> 15;
|
|
|
|
size = (C_Size + 1ul) * (1ul << (MULT + 2ul)) * (1ul << R_LEN);
|
|
|
|
|
|
|
|
pSD->diskSize = size / 1024ul;
|
|
|
|
pSD->totalSectorN = size / 512ul;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
pSD->sectorSize = (int)512;
|
|
|
|
// printf("The size is %d KB\n", pSD->diskSize);
|
|
|
|
}
|
|
|
|
|
|
|
|
/** @endcond HIDDEN_SYMBOLS */
|
|
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief This function use to reset SD function and select card detection source and pin.
|
|
|
|
*
|
|
|
|
* @param[in] sdh Select SDH0 or SDH1.
|
|
|
|
* @param[in] u32CardDetSrc Select card detection pin from GPIO or DAT3 pin. ( \ref CardDetect_From_GPIO / \ref CardDetect_From_DAT3)
|
|
|
|
*
|
|
|
|
* @return None
|
|
|
|
*/
|
2021-06-16 16:53:41 +08:00
|
|
|
void SDH_Open(SDH_T *sdh, SDH_INFO_T *pSD, uint32_t u32CardDetSrc)
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
|
|
|
volatile int i;
|
2021-06-16 16:53:41 +08:00
|
|
|
|
2021-06-21 22:04:34 +08:00
|
|
|
uint32_t u32INTEN_CDSRC_Msk = 0;
|
|
|
|
uint32_t u32INTSTS_CDIF_Msk = 0;
|
|
|
|
uint32_t u32INTEN_CDIEN_Msk = 0;
|
2021-06-29 00:37:32 +08:00
|
|
|
uint32_t u32CTL_CLKKEEP_Msk = 0;
|
2021-06-16 16:53:41 +08:00
|
|
|
|
2021-06-21 22:04:34 +08:00
|
|
|
if (u32CardDetSrc & SD_PORT0)
|
2021-06-16 16:53:41 +08:00
|
|
|
{
|
|
|
|
u32INTEN_CDSRC_Msk = SDH_INTEN_CDSRC_Msk;
|
|
|
|
u32INTSTS_CDIF_Msk = SDH_INTSTS_CDIF_Msk;
|
|
|
|
u32INTEN_CDIEN_Msk = SDH_INTEN_CDIEN_Msk;
|
2021-06-29 00:37:32 +08:00
|
|
|
u32CTL_CLKKEEP_Msk = SDH_CTL_CLKKEEP0_Msk;
|
2021-06-16 16:53:41 +08:00
|
|
|
}
|
2021-06-21 22:04:34 +08:00
|
|
|
else if (u32CardDetSrc & SD_PORT1)
|
2021-06-16 16:53:41 +08:00
|
|
|
{
|
|
|
|
u32INTEN_CDSRC_Msk = SDH_INTEN_CDSRC1_Msk;
|
|
|
|
u32INTSTS_CDIF_Msk = SDH_INTSTS_CDIF1_Msk;
|
|
|
|
u32INTEN_CDIEN_Msk = SDH_INTEN_CDIEN1_Msk;
|
2021-06-29 00:37:32 +08:00
|
|
|
u32CTL_CLKKEEP_Msk = SDH_CTL_CLKKEEP1_Msk;
|
2021-06-16 16:53:41 +08:00
|
|
|
}
|
|
|
|
|
2021-06-29 00:37:32 +08:00
|
|
|
// Enable DMAC
|
2021-05-12 19:15:17 +08:00
|
|
|
sdh->DMACTL = SDH_DMACTL_DMARST_Msk;
|
|
|
|
while ((sdh->DMACTL & SDH_DMACTL_DMARST_Msk) == SDH_DMACTL_DMARST_Msk)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
sdh->DMACTL = SDH_DMACTL_DMAEN_Msk;
|
|
|
|
|
2021-06-29 00:37:32 +08:00
|
|
|
// Reset Global
|
2021-05-12 19:15:17 +08:00
|
|
|
sdh->GCTL = SDH_GCTL_GCTLRST_Msk | SDH_GCTL_SDEN_Msk;
|
|
|
|
while ((sdh->GCTL & SDH_GCTL_GCTLRST_Msk) == SDH_GCTL_GCTLRST_Msk)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2021-06-29 00:37:32 +08:00
|
|
|
if (sdh == SDH1)
|
|
|
|
{
|
|
|
|
/* Enable Power, 0: Enable, 1:Disable */
|
|
|
|
if (u32CardDetSrc & SD_PORT0)
|
|
|
|
{
|
|
|
|
sdh->ECTL &= ~SDH_ECTL_POWEROFF0_Msk;
|
|
|
|
}
|
|
|
|
else if (u32CardDetSrc & SD_PORT1)
|
|
|
|
{
|
|
|
|
sdh->ECTL &= ~SDH_ECTL_POWEROFF1_Msk;
|
|
|
|
}
|
|
|
|
/* disable SD clock output */
|
|
|
|
sdh->CTL &= ~(0xFF | u32CTL_CLKKEEP_Msk);
|
|
|
|
}
|
|
|
|
|
|
|
|
sdh->CTL |= SDH_CTL_CTLRST_Msk;
|
|
|
|
while ((sdh->CTL & SDH_CTL_CTLRST_Msk) == SDH_CTL_CTLRST_Msk)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
memset(pSD, 0, sizeof(SDH_INFO_T));
|
2021-05-12 19:15:17 +08:00
|
|
|
if (sdh == SDH0)
|
|
|
|
{
|
2021-06-16 16:53:41 +08:00
|
|
|
pSD->dmabuf = (unsigned char *)((uint32_t)_SDH0_ucSDHCBuffer | 0x80000000);
|
|
|
|
pSD->IsCardInsert = 1;
|
2021-05-12 19:15:17 +08:00
|
|
|
}
|
|
|
|
else if (sdh == SDH1)
|
|
|
|
{
|
2021-06-16 16:53:41 +08:00
|
|
|
pSD->dmabuf = (unsigned char *)((uint32_t)_SDH1_ucSDHCBuffer | 0x80000000);
|
2021-05-12 19:15:17 +08:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
// enable SD
|
2021-05-12 19:15:17 +08:00
|
|
|
sdh->GCTL = SDH_GCTL_SDEN_Msk;
|
|
|
|
|
|
|
|
if ((u32CardDetSrc & CardDetect_From_DAT3) == CardDetect_From_DAT3)
|
|
|
|
{
|
2021-06-21 22:04:34 +08:00
|
|
|
sdh->INTEN &= ~u32INTEN_CDSRC_Msk;
|
2021-05-12 19:15:17 +08:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2021-06-21 22:04:34 +08:00
|
|
|
sdh->INTEN |= u32INTEN_CDSRC_Msk;
|
2021-05-12 19:15:17 +08:00
|
|
|
}
|
2021-06-16 16:53:41 +08:00
|
|
|
|
2021-05-12 19:15:17 +08:00
|
|
|
for (i = 0; i < 0x100; i++);
|
2021-06-16 16:53:41 +08:00
|
|
|
|
|
|
|
sdh->INTSTS = u32INTSTS_CDIF_Msk;
|
|
|
|
sdh->INTEN |= u32INTEN_CDIEN_Msk;
|
2021-05-12 19:15:17 +08:00
|
|
|
}
|
|
|
|
|
2021-06-29 00:37:32 +08:00
|
|
|
|
|
|
|
|
2021-05-12 19:15:17 +08:00
|
|
|
/**
|
|
|
|
* @brief This function use to initial SD card.
|
|
|
|
*
|
|
|
|
* @param[in] sdh Select SDH0 or SDH1.
|
|
|
|
*
|
|
|
|
* @return None
|
|
|
|
*
|
|
|
|
* @details This function is used to initial SD card.
|
|
|
|
* SD initial state needs 400KHz clock output, driver will use HIRC for SD initial clock source.
|
|
|
|
* And then switch back to the user's setting.
|
|
|
|
*/
|
2021-06-16 16:53:41 +08:00
|
|
|
uint32_t SDH_Probe(SDH_T *sdh, SDH_INFO_T *pSD, uint32_t card_num)
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
|
|
|
uint32_t val;
|
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
// Disable SD host interrupt
|
2021-05-12 19:15:17 +08:00
|
|
|
sdh->GINTEN = 0ul;
|
2021-06-16 16:53:41 +08:00
|
|
|
|
2021-05-12 19:15:17 +08:00
|
|
|
sdh->CTL &= ~SDH_CTL_SDNWR_Msk;
|
|
|
|
sdh->CTL |= 0x09ul << SDH_CTL_SDNWR_Pos; /* set SDNWR = 9 */
|
|
|
|
sdh->CTL &= ~SDH_CTL_BLKCNT_Msk;
|
|
|
|
sdh->CTL |= 0x01ul << SDH_CTL_BLKCNT_Pos; /* set BLKCNT = 1 */
|
|
|
|
sdh->CTL &= ~SDH_CTL_DBW_Msk; /* SD 1-bit data bus */
|
|
|
|
|
2021-06-21 22:04:34 +08:00
|
|
|
if (sdh != SDH0) //EMMC
|
|
|
|
{
|
2021-06-16 16:53:41 +08:00
|
|
|
if (!(SDH_CardDetection(sdh, pSD, card_num)))
|
|
|
|
{
|
|
|
|
return SDH_NO_SD_CARD;
|
|
|
|
}
|
2021-06-21 22:04:34 +08:00
|
|
|
}
|
2021-05-12 19:15:17 +08:00
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
if ((val = SDH_Init(sdh, pSD)) != 0ul)
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* divider */
|
2021-06-21 22:04:34 +08:00
|
|
|
if (pSD->CardType == SDH_TYPE_MMC)
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
|
|
|
SDH_Set_clock(sdh, MMC_FREQ);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
SDH_Set_clock(sdh, SD_FREQ);
|
|
|
|
}
|
2021-06-16 16:53:41 +08:00
|
|
|
SDH_Get_SD_info(sdh, pSD);
|
2021-05-12 19:15:17 +08:00
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
if ((val = SDH_SelectCardType(sdh, pSD)) != 0ul)
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0ul;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief This function use to read data from SD card.
|
|
|
|
*
|
|
|
|
* @param[in] sdh Select SDH0 or SDH1.
|
|
|
|
* @param[out] pu8BufAddr The buffer to receive the data from SD card.
|
|
|
|
* @param[in] u32StartSec The start read sector address.
|
|
|
|
* @param[in] u32SecCount The the read sector number of data
|
|
|
|
*
|
|
|
|
* @return None
|
|
|
|
*/
|
2021-06-16 16:53:41 +08:00
|
|
|
uint32_t SDH_Read(SDH_T *sdh, SDH_INFO_T *pSD, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount)
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
|
|
|
uint32_t volatile bIsSendCmd = FALSE, buf;
|
|
|
|
uint32_t volatile reg;
|
|
|
|
uint32_t volatile i, loop, status;
|
|
|
|
uint32_t blksize = SDH_BLOCK_SIZE;
|
|
|
|
|
|
|
|
if (u32SecCount == 0ul)
|
|
|
|
{
|
|
|
|
return SDH_SELECT_ERROR;
|
|
|
|
}
|
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
if ((status = SDH_SDCmdAndRsp(sdh, pSD, 7ul, pSD->RCA, 0ul)) != Successful)
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
|
|
|
return status;
|
|
|
|
}
|
2021-06-29 00:37:32 +08:00
|
|
|
|
2021-05-12 19:15:17 +08:00
|
|
|
SDH_CheckRB(sdh);
|
|
|
|
|
|
|
|
sdh->BLEN = blksize - 1ul; /* the actual byte count is equal to (SDBLEN+1) */
|
|
|
|
|
|
|
|
if ((pSD->CardType == SDH_TYPE_SD_HIGH) || (pSD->CardType == SDH_TYPE_EMMC))
|
|
|
|
{
|
|
|
|
sdh->CMDARG = u32StartSec;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
sdh->CMDARG = u32StartSec * blksize;
|
|
|
|
}
|
|
|
|
|
|
|
|
sdh->DMASA = (uint32_t)pu8BufAddr;
|
|
|
|
|
|
|
|
loop = u32SecCount / 255ul;
|
|
|
|
for (i = 0ul; i < loop; i++)
|
|
|
|
{
|
|
|
|
pSD->DataReadyFlag = (uint8_t)FALSE;
|
|
|
|
reg = sdh->CTL & ~SDH_CTL_CMDCODE_Msk;
|
|
|
|
reg = reg | 0xff0000ul; /* set BLK_CNT to 255 */
|
|
|
|
if (bIsSendCmd == FALSE)
|
|
|
|
{
|
|
|
|
sdh->CTL = reg | (18ul << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk);
|
|
|
|
bIsSendCmd = TRUE;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
sdh->CTL = reg | SDH_CTL_DIEN_Msk;
|
|
|
|
}
|
|
|
|
|
|
|
|
while (!pSD->DataReadyFlag)
|
|
|
|
{
|
|
|
|
if (pSD->DataReadyFlag)
|
|
|
|
{
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (pSD->IsCardInsert == FALSE)
|
|
|
|
{
|
|
|
|
return SDH_NO_SD_CARD;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) != SDH_INTSTS_CRC7_Msk) /* check CRC7 */
|
|
|
|
{
|
|
|
|
return SDH_CRC7_ERROR;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((sdh->INTSTS & SDH_INTSTS_CRC16_Msk) != SDH_INTSTS_CRC16_Msk) /* check CRC16 */
|
|
|
|
{
|
|
|
|
return SDH_CRC16_ERROR;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
loop = u32SecCount % 255ul;
|
|
|
|
if (loop != 0ul)
|
|
|
|
{
|
|
|
|
pSD->DataReadyFlag = (uint8_t)FALSE;
|
|
|
|
reg = sdh->CTL & (~SDH_CTL_CMDCODE_Msk);
|
|
|
|
reg = reg & (~SDH_CTL_BLKCNT_Msk);
|
|
|
|
reg |= (loop << 16); /* setup SDCR_BLKCNT */
|
|
|
|
|
|
|
|
if (bIsSendCmd == FALSE)
|
|
|
|
{
|
|
|
|
sdh->CTL = reg | (18ul << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk);
|
|
|
|
bIsSendCmd = TRUE;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
sdh->CTL = reg | SDH_CTL_DIEN_Msk;
|
|
|
|
}
|
|
|
|
|
|
|
|
while (!pSD->DataReadyFlag)
|
|
|
|
{
|
|
|
|
if (pSD->IsCardInsert == FALSE)
|
|
|
|
{
|
|
|
|
return SDH_NO_SD_CARD;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) != SDH_INTSTS_CRC7_Msk) /* check CRC7 */
|
|
|
|
{
|
|
|
|
return SDH_CRC7_ERROR;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((sdh->INTSTS & SDH_INTSTS_CRC16_Msk) != SDH_INTSTS_CRC16_Msk) /* check CRC16 */
|
|
|
|
{
|
|
|
|
return SDH_CRC16_ERROR;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
if (SDH_SDCmdAndRsp(sdh, pSD, 12ul, 0ul, 0ul)) /* stop command */
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
|
|
|
return SDH_CRC7_ERROR;
|
|
|
|
}
|
2021-06-29 00:37:32 +08:00
|
|
|
|
2021-05-12 19:15:17 +08:00
|
|
|
SDH_CheckRB(sdh);
|
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
SDH_SDCommand(sdh, pSD, 7ul, 0ul);
|
2021-05-12 19:15:17 +08:00
|
|
|
sdh->CTL |= SDH_CTL_CLK8OEN_Msk;
|
|
|
|
while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
return Successful;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief This function use to write data to SD card.
|
|
|
|
*
|
|
|
|
* @param[in] sdh Select SDH0 or SDH1.
|
|
|
|
* @param[in] pu8BufAddr The buffer to send the data to SD card.
|
|
|
|
* @param[in] u32StartSec The start write sector address.
|
|
|
|
* @param[in] u32SecCount The the write sector number of data.
|
|
|
|
*
|
|
|
|
* @return \ref SDH_SELECT_ERROR : u32SecCount is zero. \n
|
|
|
|
* \ref SDH_NO_SD_CARD : SD card be removed. \n
|
|
|
|
* \ref SDH_CRC_ERROR : CRC error happen. \n
|
|
|
|
* \ref SDH_CRC7_ERROR : CRC7 error happen. \n
|
|
|
|
* \ref Successful : Write data to SD card success.
|
|
|
|
*/
|
2021-06-16 16:53:41 +08:00
|
|
|
uint32_t SDH_Write(SDH_T *sdh, SDH_INFO_T *pSD, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount)
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
|
|
|
uint32_t volatile bIsSendCmd = FALSE;
|
|
|
|
uint32_t volatile reg;
|
|
|
|
uint32_t volatile i, loop, status;
|
|
|
|
|
|
|
|
if (u32SecCount == 0ul)
|
|
|
|
{
|
|
|
|
return SDH_SELECT_ERROR;
|
|
|
|
}
|
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
if ((status = SDH_SDCmdAndRsp(sdh, pSD, 7ul, pSD->RCA, 0ul)) != Successful)
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
|
|
|
SDH_CheckRB(sdh);
|
|
|
|
|
|
|
|
/* According to SD Spec v2.0, the write CMD block size MUST be 512, and the start address MUST be 512*n. */
|
|
|
|
sdh->BLEN = SDH_BLOCK_SIZE - 1ul;
|
|
|
|
|
|
|
|
if ((pSD->CardType == SDH_TYPE_SD_HIGH) || (pSD->CardType == SDH_TYPE_EMMC))
|
|
|
|
{
|
|
|
|
sdh->CMDARG = u32StartSec;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
sdh->CMDARG = u32StartSec * SDH_BLOCK_SIZE; /* set start address for SD CMD */
|
|
|
|
}
|
|
|
|
|
|
|
|
sdh->DMASA = (uint32_t)pu8BufAddr;
|
|
|
|
loop = u32SecCount / 255ul; /* the maximum block count is 0xFF=255 for register SDCR[BLK_CNT] */
|
|
|
|
for (i = 0ul; i < loop; i++)
|
|
|
|
{
|
|
|
|
pSD->DataReadyFlag = (uint8_t)FALSE;
|
|
|
|
reg = sdh->CTL & 0xff00c080;
|
|
|
|
reg = reg | 0xff0000ul; /* set BLK_CNT to 0xFF=255 */
|
|
|
|
if (!bIsSendCmd)
|
|
|
|
{
|
|
|
|
sdh->CTL = reg | (25ul << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DOEN_Msk);
|
|
|
|
bIsSendCmd = TRUE;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
sdh->CTL = reg | SDH_CTL_DOEN_Msk;
|
|
|
|
}
|
|
|
|
|
|
|
|
while (!pSD->DataReadyFlag)
|
|
|
|
{
|
|
|
|
if (pSD->IsCardInsert == FALSE)
|
|
|
|
{
|
|
|
|
return SDH_NO_SD_CARD;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((sdh->INTSTS & SDH_INTSTS_CRCIF_Msk) != 0ul)
|
|
|
|
{
|
|
|
|
sdh->INTSTS = SDH_INTSTS_CRCIF_Msk;
|
|
|
|
return SDH_CRC_ERROR;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
loop = u32SecCount % 255ul;
|
|
|
|
if (loop != 0ul)
|
|
|
|
{
|
|
|
|
pSD->DataReadyFlag = (uint8_t)FALSE;
|
|
|
|
reg = (sdh->CTL & 0xff00c080) | (loop << 16);
|
|
|
|
if (!bIsSendCmd)
|
|
|
|
{
|
|
|
|
sdh->CTL = reg | (25ul << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DOEN_Msk);
|
|
|
|
bIsSendCmd = TRUE;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
sdh->CTL = reg | SDH_CTL_DOEN_Msk;
|
|
|
|
}
|
|
|
|
|
|
|
|
while (!pSD->DataReadyFlag)
|
|
|
|
{
|
|
|
|
if (pSD->IsCardInsert == FALSE)
|
|
|
|
{
|
|
|
|
return SDH_NO_SD_CARD;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((sdh->INTSTS & SDH_INTSTS_CRCIF_Msk) != 0ul)
|
|
|
|
{
|
|
|
|
sdh->INTSTS = SDH_INTSTS_CRCIF_Msk;
|
|
|
|
return SDH_CRC_ERROR;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
sdh->INTSTS = SDH_INTSTS_CRCIF_Msk;
|
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
if (SDH_SDCmdAndRsp(sdh, pSD, 12ul, 0ul, 0ul)) /* stop command */
|
2021-05-12 19:15:17 +08:00
|
|
|
{
|
|
|
|
return SDH_CRC7_ERROR;
|
|
|
|
}
|
|
|
|
SDH_CheckRB(sdh);
|
|
|
|
|
2021-06-16 16:53:41 +08:00
|
|
|
SDH_SDCommand(sdh, pSD, 7ul, 0ul);
|
2021-05-12 19:15:17 +08:00
|
|
|
sdh->CTL |= SDH_CTL_CLK8OEN_Msk;
|
|
|
|
while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
return Successful;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*@}*/ /* end of group N9H30_SD_EXPORTED_FUNCTIONS */
|
|
|
|
|
|
|
|
/*@}*/ /* end of group N9H30_SD_Driver */
|
|
|
|
|
|
|
|
/*@}*/ /* end of group N9H30_Device_Driver */
|
|
|
|
|
|
|
|
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|