249 lines
7.3 KiB
C
249 lines
7.3 KiB
C
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/*
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* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/******************************************************************************
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* @file csi_core.h
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* @brief CSI Core Layer Header File
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* @version V1.0
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* @date 02. June 2017
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******************************************************************************/
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#ifndef _CORE_H_
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#define _CORE_H_
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#include <stdint.h>
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#include "csi_gcc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ################################## NVIC function ############################################ */
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/**
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\brief initialize the NVIC interrupt controller
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\param [in] prio_bits the priority bits of NVIC interrupt controller.
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*/
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void drv_nvic_init(uint32_t prio_bits);
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/**
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\brief Enable External Interrupt
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\details Enables a device-specific interrupt in the NVIC interrupt controller.
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\param [in] irq_num External interrupt number. Value cannot be negative.
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*/
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void drv_nvic_enable_irq(int32_t irq_num);
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/**
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\brief Disable External Interrupt
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\details Disables a device-specific interrupt in the NVIC interrupt controller.
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\param [in] irq_num External interrupt number. Value cannot be negative.
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*/
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void drv_nvic_disable_irq(int32_t irq_num);
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/**
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\brief Get Pending Interrupt
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\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
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\param [in] irq_num Interrupt number.
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\return 0 Interrupt status is not pending.
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\return 1 Interrupt status is pending.
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*/
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uint32_t drv_nvic_get_pending_irq(int32_t irq_num);
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/**
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\brief Set Pending Interrupt
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\details Sets the pending bit of an external interrupt.
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\param [in] irq_num Interrupt number. Value cannot be negative.
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*/
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void drv_nvic_set_pending_irq(int32_t irq_num);
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/**
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\brief Clear Pending Interrupt
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\details Clears the pending bit of an external interrupt.
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\param [in] irq_num External interrupt number. Value cannot be negative.
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*/
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void drv_nvic_clear_pending_irq(int32_t irq_num);
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/**
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\brief Get Active Interrupt
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\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
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\param [in] irq_num Device specific interrupt number.
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\return 0 Interrupt status is not active.
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\return 1 Interrupt status is active.
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\note irq_num must not be negative.
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*/
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uint32_t drv_nvic_get_active(int32_t irq_num);
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/**
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\brief Set Interrupt Priority
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\details Sets the priority of an interrupt.
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\note The priority cannot be set for every core interrupt.
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\param [in] irq_num Interrupt number.
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\param [in] priority Priority to set.
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*/
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void drv_nvic_set_prio(int32_t irq_num, uint32_t priority);
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/**
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\brief Get Interrupt Priority
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\details Reads the priority of an interrupt.
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The interrupt number can be positive to specify an external (device specific) interrupt,
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or negative to specify an internal (core) interrupt.
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\param [in] irq_num Interrupt number.
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\return Interrupt Priority.
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Value is aligned automatically to the implemented priority bits of the microcontroller.
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*/
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uint32_t drv_nvic_get_prio(int32_t irq_num);
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/*@} end of CSI_Core_NVICFunctions */
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/* ########################## Cache functions #################################### */
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/**
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\brief Enable I-Cache
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\details Turns on I-Cache
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*/
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void drv_icache_enable(void);
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/**
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\brief Disable I-Cache
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\details Turns off I-Cache
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*/
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void drv_icache_disable(void);
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/**
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\brief Invalidate I-Cache
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\details Invalidates I-Cache
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*/
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void drv_icache_invalid(void);
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/**
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\brief Enable D-Cache
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\details Turns on D-Cache
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\note I-Cache also turns on.
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*/
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void drv_dcache_enable(void);
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/**
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\brief Disable D-Cache
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\details Turns off D-Cache
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\note I-Cache also turns off.
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*/
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void drv_dcache_disable(void);
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/**
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\brief Invalidate D-Cache
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\details Invalidates D-Cache
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\note I-Cache also invalid
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*/
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void drv_dcache_invalid(void);
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/**
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\brief Clean D-Cache
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\details Cleans D-Cache
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\note I-Cache also cleans
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*/
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void drv_dcache_clean(void);
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/**
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\brief Clean & Invalidate D-Cache
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\details Cleans and Invalidates D-Cache
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\note I-Cache also flush.
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*/
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void drv_dcache_clean_invalid(void);
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/**
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\brief D-Cache Invalidate by address
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\details Invalidates D-Cache for the given address
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\param[in] addr address (aligned to 16-byte boundary)
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\param[in] dsize size of memory block (in number of bytes)
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*/
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void drv_dcache_invalid_range(uint32_t *addr, int32_t dsize);
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/**
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\brief D-Cache Clean by address
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\details Cleans D-Cache for the given address
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\param[in] addr address (aligned to 16-byte boundary)
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\param[in] dsize size of memory block (in number of bytes)
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*/
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void drv_dcache_clean_range(uint32_t *addr, int32_t dsize);
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/**
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\brief D-Cache Clean and Invalidate by address
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\details Cleans and invalidates D_Cache for the given address
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\param[in] addr address (aligned to 16-byte boundary)
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\param[in] dsize size of memory block (in number of bytes)
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*/
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void drv_dcache_clean_invalid_range(uint32_t *addr, int32_t dsize);
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/**
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\brief setup cacheable range Cache
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\details setup Cache range
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*/
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void drv_cache_set_range(uint32_t index, uint32_t baseAddr, uint32_t size, uint32_t enable);
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/**
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\brief Enable cache profile
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\details Turns on Cache profile
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*/
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void drv_cache_enable_profile(void);
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/**
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\brief Disable cache profile
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\details Turns off Cache profile
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*/
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void drv_cache_disable_profile(void);
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/**
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\brief Reset cache profile
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\details Reset Cache profile
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*/
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void drv_cache_reset_profile(void);
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/**
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\brief cache access times
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\details Cache access times
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\note every 256 access add 1.
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*/
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uint32_t drv_cache_get_access_time(void);
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/**
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\brief cache miss times
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\details Cache miss times
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\note every 256 miss add 1.
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*/
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uint32_t drv_cache_get_miss_time(void);
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/* ################################## SysTick function ############################################ */
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/**
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\brief CORE timer Configuration
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\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
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Counter is in free running mode to generate periodic interrupts.
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\param [in] ticks Number of ticks between two interrupts.
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\param [in] irq_num core timer Interrupt number.
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\return 0 Function succeeded.
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\return 1 Function failed.
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\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
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function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
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must contain a vendor-specific implementation of this function.
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*/
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uint32_t drv_coret_config(uint32_t ticks, int32_t irq_num);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _CORE_H_ */
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