libs/rt-thread-official
libs
/
rt-thread-official
mirror of https://github.com/RT-Thread/rt-thread.git
4
0
Fork 0
Code Issues Releases Wiki Activity
rt-thread-official/libcpu/Kconfig

315 lines
5.6 KiB
Plaintext
Raw Normal View History

[tools]fix scons --dist , menuconfig will error (#8069)
2023-09-26 11:35:27 +08:00
if ARCH_ARMV8 && ARCH_CPU_64BIT
menu "AArch64 Architecture Configuration"
config ARCH_TEXT_OFFSET
hex "Text offset"
default 0x200000
config ARCH_RAM_OFFSET
hex "RAM offset"
default 0
config ARCH_SECONDARY_CPU_STACK_SIZE
int "Secondary CPU stack size"
default 4096
config ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS
bool
default y
[libcpu/arm64] add C11 atomic ticket spinlock (#8882) * [libcpu/arm64] add C11 atomic ticket spinlock Replace the former implementation of flag-based spinlock which is unfair Besides, C11 atomic implementation is more readable (it's C anyway), and maintainable. Cause toolchain can use their builtin optimization and tune for different micro-architectures. For example armv8.5 introduces a better instruction. The compiler can help with that when it knows your target platform in support of it. Signed-off-by: Shell <smokewood@qq.com> * fixup: RT_CPUS_NR --------- Signed-off-by: Shell <smokewood@qq.com>
2024-05-16 15:45:12 +08:00
config ARCH_USING_GENERIC_CPUID
bool "Using generic cpuid implemenation"
[arm64] add hw thread self (#8942) * [libcpu] arm64: Add hardware thread_self support This patch introduces hardware-based thread self-identification for the AArch64 architecture. It optimizes thread management by using hardware registers to store and access the current thread's pointer, reducing overhead and improving overall performance. Changes include: - Added `ARCH_USING_HW_THREAD_SELF` configuration option. - Modified `rtdef.h`, `rtsched.h` to conditionally include `critical_switch_flag` based on the new config. - Updated context management in `context_gcc.S`, `cpuport.h` to support hardware-based thread self. - Enhanced `scheduler_mp.c` and `thread.c` to leverage the new hardware thread self feature. These modifications ensure better scheduling and thread handling, particularly in multi-core environments, by minimizing the software overhead associated with thread management. Signed-off-by: Shell <smokewood@qq.com> * fixup: address suggestion * fixup: rt_current_thread as global * scheduler: add cpu object for UP scheduler Also, maintain the rt_current_thread in cpu object on UP scheduler. --------- Signed-off-by: Shell <smokewood@qq.com>
2024-05-28 14:27:55 +08:00
select ARCH_USING_HW_THREAD_SELF
default y if RT_USING_OFW
[libcpu/arm64] add C11 atomic ticket spinlock (#8882) * [libcpu/arm64] add C11 atomic ticket spinlock Replace the former implementation of flag-based spinlock which is unfair Besides, C11 atomic implementation is more readable (it's C anyway), and maintainable. Cause toolchain can use their builtin optimization and tune for different micro-architectures. For example armv8.5 introduces a better instruction. The compiler can help with that when it knows your target platform in support of it. Signed-off-by: Shell <smokewood@qq.com> * fixup: RT_CPUS_NR --------- Signed-off-by: Shell <smokewood@qq.com>
2024-05-16 15:45:12 +08:00
default n
[libcpu][aarch64]memory setup using memblock (#9092) * memory setup using memblock * map pages later
2024-06-26 14:36:49 +08:00
config ARCH_HEAP_SIZE
hex "Size of system heap"
default 0x4000000
config ARCH_INIT_PAGE_SIZE
hex "Size of init page region"
default 0x200000
[tools]fix scons --dist , menuconfig will error (#8069)
2023-09-26 11:35:27 +08:00
endmenu
endif
[Kernel] Add 64bit CPU support.
2018-10-26 06:35:42 +08:00
config ARCH_CPU_64BIT
bool
sync branch rt-smart. (#6641) * Synchronize the code of the rt mart branch to the master branch. * TTY device * Add lwP code from rt-smart * Add vnode in DFS, but DFS will be re-write for rt-smart * There are three libcpu for rt-smart: * arm/cortex-a, arm/aarch64 * riscv64 Co-authored-by: Rbb666 <zhangbingru@rt-thread.com> Co-authored-by: zhkag <zhkag@foxmail.com>
2022-12-03 12:07:44 +08:00
config RT_USING_CACHE
bool
default n
[atomic]添加arm与risc-v下的常用原子操作函数 (#7053) * Update Kconfig * Update trap_gcc.S * Update bsp/hifive1/drivers/SConscript Co-authored-by: Man, Jianting (Meco) <920369182@qq.com> * Update SConscript * [atomic]提交一份arm与risc-v架构下的常用原子操作函数 * 修改变量类型 * 更新rtatomic.h与atomic_port.c * 更新rt-thread\libcpu\arm\common\atomic_port.c * 更新include/rtatomic.h与libcpu/arm/common/SConscript * 更新include/rtatomic.h * 修正格式与Kconfig * 修正格式与文件结构 * 规范文件格式与文件重命名 * 添加测试用例与CI * 添加函数声明 * 修改virt64/SConscript 添加atomic_riscv.c * 1.规范代码风格 * 2.添加RISC-V64原子指令支持 解决在RV64下编译器将32-bit运算结果扩展为64-bit 导致判断错误 * 添加C11标准库原子操作测试 --------- Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
2023-03-23 20:06:50 +08:00
config RT_USING_HW_ATOMIC
bool
default n
[Kconfig][libcpu] 增加ARCH_CPU_BIG_ENDIAN (#5547) * [cpu] 增加ARCH_CPU_BIG_ENDIAN - 之前RT_USING_BIG_ENDIAN的命名并不合理，予以替换为ARCH_CPU_BIG_ENDIAN - 删除一处多余的ARCH_CPU_64BIT - 整理了libcpu/Kconfig的格式 * [libcpu][Kconfig] Cortex-M4&7 select ARCH_ARM_CORTEX_FPU * revert last commit
2022-01-25 15:00:47 +08:00
config ARCH_CPU_BIG_ENDIAN
bool
sync branch rt-smart. (#6641) * Synchronize the code of the rt mart branch to the master branch. * TTY device * Add lwP code from rt-smart * Add vnode in DFS, but DFS will be re-write for rt-smart * There are three libcpu for rt-smart: * arm/cortex-a, arm/aarch64 * riscv64 Co-authored-by: Rbb666 <zhangbingru@rt-thread.com> Co-authored-by: zhkag <zhkag@foxmail.com>
2022-12-03 12:07:44 +08:00
config ARCH_ARM_BOOTWITH_FLUSH_CACHE
bool
default n
config ARCH_CPU_STACK_GROWS_UPWARD
Update Kconfig. 1. Add IPADDR/GWADDR etc; 2. Add Kconfig for libcpu.
2017-10-31 09:54:23 +08:00
bool
sync branch rt-smart. (#6641) * Synchronize the code of the rt mart branch to the master branch. * TTY device * Add lwP code from rt-smart * Add vnode in DFS, but DFS will be re-write for rt-smart * There are three libcpu for rt-smart: * arm/cortex-a, arm/aarch64 * riscv64 Co-authored-by: Rbb666 <zhangbingru@rt-thread.com> Co-authored-by: zhkag <zhkag@foxmail.com>
2022-12-03 12:07:44 +08:00
default n
Update Kconfig. 1. Add IPADDR/GWADDR etc; 2. Add Kconfig for libcpu.
2017-10-31 09:54:23 +08:00
对CM3,CM4,CM7 自动开启RT_USING_CPU_FFS
2019-05-28 21:30:45 +08:00
config RT_USING_CPU_FFS
bool
default n
sync branch rt-smart. (#6641) * Synchronize the code of the rt mart branch to the master branch. * TTY device * Add lwP code from rt-smart * Add vnode in DFS, but DFS will be re-write for rt-smart * There are three libcpu for rt-smart: * arm/cortex-a, arm/aarch64 * riscv64 Co-authored-by: Rbb666 <zhangbingru@rt-thread.com> Co-authored-by: zhkag <zhkag@foxmail.com>
2022-12-03 12:07:44 +08:00
config ARCH_MM_MMU
bool
config ARCH_MM_MPU
bool
config ARCH_ARM
bool
Update Kconfig. 1. Add IPADDR/GWADDR etc; 2. Add Kconfig for libcpu.
2017-10-31 09:54:23 +08:00
config ARCH_ARM_CORTEX_M
bool
select ARCH_ARM
[bsp][renesas]Add cortex-r52 rzt2m adaptation
2024-04-11 08:47:53 +08:00
config ARCH_ARM_CORTEX_R
bool
select ARCH_ARM
[BSP] Enable memory pool for i.MXRT1050-EVK.
2018-09-22 22:22:18 +08:00
config ARCH_ARM_CORTEX_FPU
bool
支持只运行在安全模式下 (#6115) * [cpu][cm33] Support running in secure mode * [bsp][lpc55sxx] Using the cortex cm33
2022-06-29 14:08:57 +08:00
config ARCH_ARM_CORTEX_SECURE
bool
Update Kconfig. 1. Add IPADDR/GWADDR etc; 2. Add Kconfig for libcpu.
2017-10-31 09:54:23 +08:00
config ARCH_ARM_CORTEX_M0
bool
select ARCH_ARM_CORTEX_M
config ARCH_ARM_CORTEX_M3
bool
select ARCH_ARM_CORTEX_M
对CM3,CM4,CM7 自动开启RT_USING_CPU_FFS
2019-05-28 21:30:45 +08:00
select RT_USING_CPU_FFS
[atomic]添加arm与risc-v下的常用原子操作函数 (#7053) * Update Kconfig * Update trap_gcc.S * Update bsp/hifive1/drivers/SConscript Co-authored-by: Man, Jianting (Meco) <920369182@qq.com> * Update SConscript * [atomic]提交一份arm与risc-v架构下的常用原子操作函数 * 修改变量类型 * 更新rtatomic.h与atomic_port.c * 更新rt-thread\libcpu\arm\common\atomic_port.c * 更新include/rtatomic.h与libcpu/arm/common/SConscript * 更新include/rtatomic.h * 修正格式与Kconfig * 修正格式与文件结构 * 规范文件格式与文件重命名 * 添加测试用例与CI * 添加函数声明 * 修改virt64/SConscript 添加atomic_riscv.c * 1.规范代码风格 * 2.添加RISC-V64原子指令支持 解决在RV64下编译器将32-bit运算结果扩展为64-bit 导致判断错误 * 添加C11标准库原子操作测试 --------- Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
2023-03-23 20:06:50 +08:00
select RT_USING_HW_ATOMIC
Update Kconfig. 1. Add IPADDR/GWADDR etc; 2. Add Kconfig for libcpu.
2017-10-31 09:54:23 +08:00
config ARCH_ARM_MPU
bool
depends on ARCH_ARM
sync branch rt-smart. (#6641) * Synchronize the code of the rt mart branch to the master branch. * TTY device * Add lwP code from rt-smart * Add vnode in DFS, but DFS will be re-write for rt-smart * There are three libcpu for rt-smart: * arm/cortex-a, arm/aarch64 * riscv64 Co-authored-by: Rbb666 <zhangbingru@rt-thread.com> Co-authored-by: zhkag <zhkag@foxmail.com>
2022-12-03 12:07:44 +08:00
select ARCH_MM_MPU
Update Kconfig. 1. Add IPADDR/GWADDR etc; 2. Add Kconfig for libcpu.
2017-10-31 09:54:23 +08:00
config ARCH_ARM_CORTEX_M4
bool
select ARCH_ARM_CORTEX_M
对CM3,CM4,CM7 自动开启RT_USING_CPU_FFS
2019-05-28 21:30:45 +08:00
select RT_USING_CPU_FFS
[atomic]添加arm与risc-v下的常用原子操作函数 (#7053) * Update Kconfig * Update trap_gcc.S * Update bsp/hifive1/drivers/SConscript Co-authored-by: Man, Jianting (Meco) <920369182@qq.com> * Update SConscript * [atomic]提交一份arm与risc-v架构下的常用原子操作函数 * 修改变量类型 * 更新rtatomic.h与atomic_port.c * 更新rt-thread\libcpu\arm\common\atomic_port.c * 更新include/rtatomic.h与libcpu/arm/common/SConscript * 更新include/rtatomic.h * 修正格式与Kconfig * 修正格式与文件结构 * 规范文件格式与文件重命名 * 添加测试用例与CI * 添加函数声明 * 修改virt64/SConscript 添加atomic_riscv.c * 1.规范代码风格 * 2.添加RISC-V64原子指令支持 解决在RV64下编译器将32-bit运算结果扩展为64-bit 导致判断错误 * 添加C11标准库原子操作测试 --------- Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
2023-03-23 20:06:50 +08:00
select RT_USING_HW_ATOMIC
Update Kconfig. 1. Add IPADDR/GWADDR etc; 2. Add Kconfig for libcpu.
2017-10-31 09:54:23 +08:00
config ARCH_ARM_CORTEX_M7
bool
select ARCH_ARM_CORTEX_M
对CM3,CM4,CM7 自动开启RT_USING_CPU_FFS
2019-05-28 21:30:45 +08:00
select RT_USING_CPU_FFS
sync branch rt-smart. (#6641) * Synchronize the code of the rt mart branch to the master branch. * TTY device * Add lwP code from rt-smart * Add vnode in DFS, but DFS will be re-write for rt-smart * There are three libcpu for rt-smart: * arm/cortex-a, arm/aarch64 * riscv64 Co-authored-by: Rbb666 <zhangbingru@rt-thread.com> Co-authored-by: zhkag <zhkag@foxmail.com>
2022-12-03 12:07:44 +08:00
select RT_USING_CACHE
[libcpu][renesas]add cortex-m85 && ek-ra8m1 adapt
2023-10-17 17:20:54 +08:00
config ARCH_ARM_CORTEX_M85
bool
select ARCH_ARM_CORTEX_M
select RT_USING_CPU_FFS
[atomic]添加arm与risc-v下的常用原子操作函数 (#7053) * Update Kconfig * Update trap_gcc.S * Update bsp/hifive1/drivers/SConscript Co-authored-by: Man, Jianting (Meco) <920369182@qq.com> * Update SConscript * [atomic]提交一份arm与risc-v架构下的常用原子操作函数 * 修改变量类型 * 更新rtatomic.h与atomic_port.c * 更新rt-thread\libcpu\arm\common\atomic_port.c * 更新include/rtatomic.h与libcpu/arm/common/SConscript * 更新include/rtatomic.h * 修正格式与Kconfig * 修正格式与文件结构 * 规范文件格式与文件重命名 * 添加测试用例与CI * 添加函数声明 * 修改virt64/SConscript 添加atomic_riscv.c * 1.规范代码风格 * 2.添加RISC-V64原子指令支持 解决在RV64下编译器将32-bit运算结果扩展为64-bit 导致判断错误 * 添加C11标准库原子操作测试 --------- Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
2023-03-23 20:06:50 +08:00
select RT_USING_HW_ATOMIC
Update Kconfig. 1. Add IPADDR/GWADDR etc; 2. Add Kconfig for libcpu.
2017-10-31 09:54:23 +08:00
[libcpu/Kconfig] add ARCH_ARM_CORTEX_M23 define (#7895)
2023-08-01 00:00:49 +08:00
config ARCH_ARM_CORTEX_M23
bool
select ARCH_ARM_CORTEX_M
select RT_USING_HW_ATOMIC
[libcpu] Add CM33 (#5761)
2022-04-01 22:45:11 +08:00
config ARCH_ARM_CORTEX_M33
bool
select ARCH_ARM_CORTEX_M
select RT_USING_CPU_FFS
[atomic]添加arm与risc-v下的常用原子操作函数 (#7053) * Update Kconfig * Update trap_gcc.S * Update bsp/hifive1/drivers/SConscript Co-authored-by: Man, Jianting (Meco) <920369182@qq.com> * Update SConscript * [atomic]提交一份arm与risc-v架构下的常用原子操作函数 * 修改变量类型 * 更新rtatomic.h与atomic_port.c * 更新rt-thread\libcpu\arm\common\atomic_port.c * 更新include/rtatomic.h与libcpu/arm/common/SConscript * 更新include/rtatomic.h * 修正格式与Kconfig * 修正格式与文件结构 * 规范文件格式与文件重命名 * 添加测试用例与CI * 添加函数声明 * 修改virt64/SConscript 添加atomic_riscv.c * 1.规范代码风格 * 2.添加RISC-V64原子指令支持 解决在RV64下编译器将32-bit运算结果扩展为64-bit 导致判断错误 * 添加C11标准库原子操作测试 --------- Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
2023-03-23 20:06:50 +08:00
select RT_USING_HW_ATOMIC
[libcpu] Add CM33 (#5761)
2022-04-01 22:45:11 +08:00
Update Kconfig. 1. Add IPADDR/GWADDR etc; 2. Add Kconfig for libcpu.
2017-10-31 09:54:23 +08:00
config ARCH_ARM_CORTEX_R
bool
select ARCH_ARM
[atomic]添加arm与risc-v下的常用原子操作函数 (#7053) * Update Kconfig * Update trap_gcc.S * Update bsp/hifive1/drivers/SConscript Co-authored-by: Man, Jianting (Meco) <920369182@qq.com> * Update SConscript * [atomic]提交一份arm与risc-v架构下的常用原子操作函数 * 修改变量类型 * 更新rtatomic.h与atomic_port.c * 更新rt-thread\libcpu\arm\common\atomic_port.c * 更新include/rtatomic.h与libcpu/arm/common/SConscript * 更新include/rtatomic.h * 修正格式与Kconfig * 修正格式与文件结构 * 规范文件格式与文件重命名 * 添加测试用例与CI * 添加函数声明 * 修改virt64/SConscript 添加atomic_riscv.c * 1.规范代码风格 * 2.添加RISC-V64原子指令支持 解决在RV64下编译器将32-bit运算结果扩展为64-bit 导致判断错误 * 添加C11标准库原子操作测试 --------- Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
2023-03-23 20:06:50 +08:00
select RT_USING_HW_ATOMIC
Update Kconfig. 1. Add IPADDR/GWADDR etc; 2. Add Kconfig for libcpu.
2017-10-31 09:54:23 +08:00
[bsp][renesas]Add cortex-r52 rzt2m adaptation
2024-04-11 08:47:53 +08:00
config ARCH_ARM_CORTEX_R52
bool
select ARCH_ARM_CORTEX_R
Update Kconfig. 1. Add IPADDR/GWADDR etc; 2. Add Kconfig for libcpu.
2017-10-31 09:54:23 +08:00
config ARCH_ARM_MMU
bool
sync branch rt-smart. (#6641) * Synchronize the code of the rt mart branch to the master branch. * TTY device * Add lwP code from rt-smart * Add vnode in DFS, but DFS will be re-write for rt-smart * There are three libcpu for rt-smart: * arm/cortex-a, arm/aarch64 * riscv64 Co-authored-by: Rbb666 <zhangbingru@rt-thread.com> Co-authored-by: zhkag <zhkag@foxmail.com>
2022-12-03 12:07:44 +08:00
select RT_USING_CACHE
select ARCH_MM_MMU
Update Kconfig. 1. Add IPADDR/GWADDR etc; 2. Add Kconfig for libcpu.
2017-10-31 09:54:23 +08:00
depends on ARCH_ARM
[rt-smart] 弱化 RT_USING_LWP，使用 RT_USING_SMART 作为宏配置 (#6740) * [dfs] sync cromfs * [rt-smart]Weaken RT_USING_LWP, use RT_USING_SMART as macro configuration * [format] fix some format issue.
2022-12-16 18:38:28 +08:00
if RT_USING_SMART
[debug] 整理debug宏并增加RT_DEBUGING_CONTEXT (#7805)
2023-07-22 10:36:42 +08:00
config KERNEL_VADDR_START
hex "The virtural address of kernel start"
default 0xffff000000000000 if ARCH_ARMV8
default 0xc0000000 if ARCH_ARM
[libcpu] rv64: support for ARCH_REMAP_KERNEL (#9067) * [libcpu] support for ARCH_REMAP_KERNEL These changes introduce support for the ARCH_REMAP_KERNEL configuration, which isolates kernel space in high virtual address regions. This feature is necessary to enhance memory protection and management by segregating user and kernel spaces more effectively. Changes: - Updated conditional macros to check for ARCH_REMAP_KERNEL instead of ARCH_KERNEL_IN_HIGH_VA in board initialization files to reflect the new configuration option. - Modified qemu-virt64-riscv Kconfig and SConstruct files to include and utilize ARCH_REMAP_KERNEL. - Created a new linker script `link_smart.lds` for smart linking in qemu-virt64-riscv. - Updated rtconfig.py to use a more flexible execution path setup. - Enhanced user address space definitions in `lwp_arch.h` to support the new virtual address mappings. - Adjusted kernel memory initialization and mapping logic in `c906/mmu.c` and `virt64/mmu.c` to account for high virtual address regions. - Added Kconfig option to enable ARCH_REMAP_KERNEL for RISCV64 architectures. - Enhanced memory setup functions to support new mapping scheme, including updates to early page table setup and address relocation logic. These modifications ensure that the system can utilize high memory addresses for the kernel, improving memory isolation and system stability. Signed-off-by: Shell <smokewood@qq.com> * fixup: CI run failed * bsp: default config without using smart * fixup: static checks * restore rt_hw_mmu_kernel_map_init for D1 --------- Signed-off-by: Shell <smokewood@qq.com>
2024-06-18 11:15:59 +08:00
default 0xffffffc000000000 if ARCH_RISCV && ARCH_REMAP_KERNEL
[debug] 整理debug宏并增加RT_DEBUGING_CONTEXT (#7805)
2023-07-22 10:36:42 +08:00
default 0x80000000 if ARCH_RISCV
depends on ARCH_MM_MMU
config RT_IOREMAP_LATE
bool "Support to create IO mapping in the kernel address space after system initlalization."
default n
depends on ARCH_ARM_CORTEX_A
depends on ARCH_MM_MMU
[rt-smart] 弱化 RT_USING_LWP，使用 RT_USING_SMART 作为宏配置 (#6740) * [dfs] sync cromfs * [rt-smart]Weaken RT_USING_LWP, use RT_USING_SMART as macro configuration * [format] fix some format issue.
2022-12-16 18:38:28 +08:00
endif
sync branch rt-smart. (#6641) * Synchronize the code of the rt mart branch to the master branch. * TTY device * Add lwP code from rt-smart * Add vnode in DFS, but DFS will be re-write for rt-smart * There are three libcpu for rt-smart: * arm/cortex-a, arm/aarch64 * riscv64 Co-authored-by: Rbb666 <zhangbingru@rt-thread.com> Co-authored-by: zhkag <zhkag@foxmail.com>
2022-12-03 12:07:44 +08:00
[libcpu] Add ARCH_ARM_ARM9/11 type
2017-12-19 17:39:23 +08:00
config ARCH_ARM_ARM9
bool
select ARCH_ARM
config ARCH_ARM_ARM11
bool
select ARCH_ARM
[BSP] add i.MX 6UL BSP
2017-11-01 13:30:17 +08:00
config ARCH_ARM_CORTEX_A
Update Kconfig. 1. Add IPADDR/GWADDR etc; 2. Add Kconfig for libcpu.
2017-10-31 09:54:23 +08:00
bool
select ARCH_ARM
Add ADT Kconfig and fix MMU kconfig issue in Cortex-A (#6901) * Add ADT Kconfig and fix MMU kconfig issue in Cortex-A * [BSP] enable ADT
2023-02-06 01:11:04 +08:00
select ARCH_ARM_MMU
[update] 整理cortex-a kconfig菜单，并更新相关BSP的配置。
2021-05-24 17:19:05 +08:00
select RT_USING_CPU_FFS
[atomic]添加arm与risc-v下的常用原子操作函数 (#7053) * Update Kconfig * Update trap_gcc.S * Update bsp/hifive1/drivers/SConscript Co-authored-by: Man, Jianting (Meco) <920369182@qq.com> * Update SConscript * [atomic]提交一份arm与risc-v架构下的常用原子操作函数 * 修改变量类型 * 更新rtatomic.h与atomic_port.c * 更新rt-thread\libcpu\arm\common\atomic_port.c * 更新include/rtatomic.h与libcpu/arm/common/SConscript * 更新include/rtatomic.h * 修正格式与Kconfig * 修正格式与文件结构 * 规范文件格式与文件重命名 * 添加测试用例与CI * 添加函数声明 * 修改virt64/SConscript 添加atomic_riscv.c * 1.规范代码风格 * 2.添加RISC-V64原子指令支持 解决在RV64下编译器将32-bit运算结果扩展为64-bit 导致判断错误 * 添加C11标准库原子操作测试 --------- Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
2023-03-23 20:06:50 +08:00
select RT_USING_HW_ATOMIC
Update Kconfig. 1. Add IPADDR/GWADDR etc; 2. Add Kconfig for libcpu.
2017-10-31 09:54:23 +08:00
[add] 添加gicv3中断控制器代码，更新menuconfig配置选项与utest的config.h
2021-05-01 19:15:37 +08:00
if ARCH_ARM_CORTEX_A
config RT_SMP_AUTO_BOOT
bool
default n
[update] 整理cortex-a kconfig菜单，并更新相关BSP的配置。
2021-05-24 17:19:05 +08:00
config RT_USING_GIC_V2
bool
default n
[add] 添加gicv3中断控制器代码，更新menuconfig配置选项与utest的config.h
2021-05-01 19:15:37 +08:00
[update] 整理cortex-a kconfig菜单，并更新相关BSP的配置。
2021-05-24 17:19:05 +08:00
config RT_USING_GIC_V3
bool
default n
[add] 添加gicv3中断控制器代码，更新menuconfig配置选项与utest的config.h
2021-05-01 19:15:37 +08:00
[update] 整理cortex-a kconfig菜单，并更新相关BSP的配置。
2021-05-24 17:19:05 +08:00
config RT_NO_USING_GIC
bool
default y if !RT_USING_GIC_V2 && !RT_USING_GIC_V3
[add] 添加gicv3中断控制器代码，更新menuconfig配置选项与utest的config.h
2021-05-01 19:15:37 +08:00
endif
[BSP] add i.MX 6UL BSP
2017-11-01 13:30:17 +08:00
config ARCH_ARM_CORTEX_A5
bool
select ARCH_ARM_CORTEX_A
Update Kconfig. 1. Add IPADDR/GWADDR etc; 2. Add Kconfig for libcpu.
2017-10-31 09:54:23 +08:00
config ARCH_ARM_CORTEX_A7
bool
[BSP] add i.MX 6UL BSP
2017-11-01 13:30:17 +08:00
select ARCH_ARM_CORTEX_A
Update Kconfig. 1. Add IPADDR/GWADDR etc; 2. Add Kconfig for libcpu.
2017-10-31 09:54:23 +08:00
config ARCH_ARM_CORTEX_A8
bool
[BSP] add i.MX 6UL BSP
2017-11-01 13:30:17 +08:00
select ARCH_ARM_CORTEX_A
Update Kconfig. 1. Add IPADDR/GWADDR etc; 2. Add Kconfig for libcpu.
2017-10-31 09:54:23 +08:00
config ARCH_ARM_CORTEX_A9
bool
[BSP] add i.MX 6UL BSP
2017-11-01 13:30:17 +08:00
select ARCH_ARM_CORTEX_A
Update Kconfig. 1. Add IPADDR/GWADDR etc; 2. Add Kconfig for libcpu.
2017-10-31 09:54:23 +08:00
AMP-step3: 添加conifg ARCH_ARM_CORTEX_A55， rt_hw_cpu_id_set 适配A55架构, 添加aarch64 rt_… (#7628)
2023-06-11 07:06:16 +08:00
config ARCH_ARM_CORTEX_A55
bool
select ARCH_ARM_CORTEX_A
sync branch rt-smart. (#6641) * Synchronize the code of the rt mart branch to the master branch. * TTY device * Add lwP code from rt-smart * Add vnode in DFS, but DFS will be re-write for rt-smart * There are three libcpu for rt-smart: * arm/cortex-a, arm/aarch64 * riscv64 Co-authored-by: Rbb666 <zhangbingru@rt-thread.com> Co-authored-by: zhkag <zhkag@foxmail.com>
2022-12-03 12:07:44 +08:00
config ARCH_ARM_SECURE_MODE
bool "Running in secure mode [ARM Cortex-A]"
default n
depends on ARCH_ARM_CORTEX_A
config RT_BACKTRACE_FUNCTION_NAME
bool "To show function name when backtrace."
default n
depends on ARCH_ARM_CORTEX_A
rename raspi4 to raspi4-64
2020-05-25 17:46:48 +08:00
config ARCH_ARMV8
bool
sync branch rt-smart. (#6641) * Synchronize the code of the rt mart branch to the master branch. * TTY device * Add lwP code from rt-smart * Add vnode in DFS, but DFS will be re-write for rt-smart * There are three libcpu for rt-smart: * arm/cortex-a, arm/aarch64 * riscv64 Co-authored-by: Rbb666 <zhangbingru@rt-thread.com> Co-authored-by: zhkag <zhkag@foxmail.com>
2022-12-03 12:07:44 +08:00
select ARCH_ARM
[smart/aarch64] code sync (#6750) * [smart/aarch64] sync aarch64
2022-12-20 17:49:37 +08:00
select ARCH_ARM_MMU
🎈 perf: perf rt_hw_interrupt_disable/enable (#8042) Signed-off-by: Shell <smokewood@qq.com> Co-authored-by: Shell <smokewood@qq.com>
2023-10-25 20:31:25 +08:00
select RT_USING_CPU_FFS
rename raspi4 to raspi4-64
2020-05-25 17:46:48 +08:00
Update Kconfig. 1. Add IPADDR/GWADDR etc; 2. Add Kconfig for libcpu.
2017-10-31 09:54:23 +08:00
config ARCH_MIPS
bool
add ls2k bsp
2020-04-05 13:29:29 +08:00
config ARCH_MIPS64
bool
[Kconfig][libcpu] 增加ARCH_CPU_BIG_ENDIAN (#5547) * [cpu] 增加ARCH_CPU_BIG_ENDIAN - 之前RT_USING_BIG_ENDIAN的命名并不合理，予以替换为ARCH_CPU_BIG_ENDIAN - 删除一处多余的ARCH_CPU_64BIT - 整理了libcpu/Kconfig的格式 * [libcpu][Kconfig] Cortex-M4&7 select ARCH_ARM_CORTEX_FPU * revert last commit
2022-01-25 15:00:47 +08:00
select ARCH_CPU_64BIT
add ls2k bsp
2020-04-05 13:29:29 +08:00
Update Kconfig. 1. Add IPADDR/GWADDR etc; 2. Add Kconfig for libcpu.
2017-10-31 09:54:23 +08:00
config ARCH_MIPS_XBURST
bool
select ARCH_MIPS
config ARCH_ANDES
bool
config ARCH_CSKY
bool
config ARCH_POWERPC
bool
config ARCH_RISCV
bool
[Kernel] Add 64bit CPU support.
2018-10-26 06:35:42 +08:00
config ARCH_RISCV_FPU
bool
feat: libcpu/risc-v: unify context on c906, virt64 Changes: - added config for NEW_CTX_SWITCH - used new context on c906 sched switch routine - update _rt_hw_stack_init to fit into NEW_CTX_SWITCH - separated vector ctx from the generic Signed-off-by: Shell <smokewood@qq.com>
2024-09-02 16:38:42 +08:00
config ARCH_RISCV_VECTOR
bool
[libcpu/risc-v][K210] add FPU support
2020-11-20 12:05:37 +08:00
config ARCH_RISCV_FPU_S
select ARCH_RISCV_FPU
bool
config ARCH_RISCV_FPU_D
select ARCH_RISCV_FPU
bool
[Kernel] Add 64bit CPU support.
2018-10-26 06:35:42 +08:00
config ARCH_RISCV32
select ARCH_RISCV
bool
config ARCH_RISCV64
select ARCH_RISCV
select ARCH_CPU_64BIT
bool
[libcpu/rv64] feat: unify tick.c The changes unify the tick.c implementations for all risc-v64 architectures, leveraging the CPUTIME feature. This refactoring was necessary to streamline the codebase, and ensure consistent timer handling across different platforms. Changes: - Updated `Kconfig` in `bsp/cvitek/cv18xx_risc-v` to fix formatting issues. - Updated .config for BSPs to update `CPUTIME_TIMER_FREQ` - Updated header of for API `riscv_cputime_init` - Initialized riscv timer on `rt_hw_tick_init` - Refactored `tick.c` and `tick.h` in `libcpu/risc-v/t-head/c906` and `libcpu/risc-v/virt64`: - Replaced direct use of `rdtime` with `clock_cpu_gettime`. - Removed redundant timer frequency definitions. - Added static assertions to check the value of `CPUTIME_TIMER_FREQ`. - Initialized `tick_cycles` based on `CPUTIME_TIMER_FREQ`. - Integrated `ktime` support for tick initialization. Signed-off-by: Shell <smokewood@qq.com> Reviewed-on: https://github.com/RT-Thread/rt-thread/pull/9164 Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-15 12:06:17 +08:00
if ARCH_RISCV64
feat: libcpu/risc-v: unify context on c906, virt64 Changes: - added config for NEW_CTX_SWITCH - used new context on c906 sched switch routine - update _rt_hw_stack_init to fit into NEW_CTX_SWITCH - separated vector ctx from the generic Signed-off-by: Shell <smokewood@qq.com>
2024-09-02 16:38:42 +08:00
config ARCH_USING_NEW_CTX_SWITCH
bool
default y
[libcpu/rv64] feat: unify tick.c The changes unify the tick.c implementations for all risc-v64 architectures, leveraging the CPUTIME feature. This refactoring was necessary to streamline the codebase, and ensure consistent timer handling across different platforms. Changes: - Updated `Kconfig` in `bsp/cvitek/cv18xx_risc-v` to fix formatting issues. - Updated .config for BSPs to update `CPUTIME_TIMER_FREQ` - Updated header of for API `riscv_cputime_init` - Initialized riscv timer on `rt_hw_tick_init` - Refactored `tick.c` and `tick.h` in `libcpu/risc-v/t-head/c906` and `libcpu/risc-v/virt64`: - Replaced direct use of `rdtime` with `clock_cpu_gettime`. - Removed redundant timer frequency definitions. - Added static assertions to check the value of `CPUTIME_TIMER_FREQ`. - Initialized `tick_cycles` based on `CPUTIME_TIMER_FREQ`. - Integrated `ktime` support for tick initialization. Signed-off-by: Shell <smokewood@qq.com> Reviewed-on: https://github.com/RT-Thread/rt-thread/pull/9164 Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-15 12:06:17 +08:00
config ARCH_USING_RISCV_COMMON64
bool
depends on ARCH_RISCV64
select RT_USING_CPUTIME
feat: libcpu/risc-v: unify context on c906, virt64 Changes: - added config for NEW_CTX_SWITCH - used new context on c906 sched switch routine - update _rt_hw_stack_init to fit into NEW_CTX_SWITCH - separated vector ctx from the generic Signed-off-by: Shell <smokewood@qq.com>
2024-09-02 16:38:42 +08:00
select ARCH_USING_NEW_CTX_SWITCH
[libcpu/rv64] feat: unify tick.c The changes unify the tick.c implementations for all risc-v64 architectures, leveraging the CPUTIME feature. This refactoring was necessary to streamline the codebase, and ensure consistent timer handling across different platforms. Changes: - Updated `Kconfig` in `bsp/cvitek/cv18xx_risc-v` to fix formatting issues. - Updated .config for BSPs to update `CPUTIME_TIMER_FREQ` - Updated header of for API `riscv_cputime_init` - Initialized riscv timer on `rt_hw_tick_init` - Refactored `tick.c` and `tick.h` in `libcpu/risc-v/t-head/c906` and `libcpu/risc-v/virt64`: - Replaced direct use of `rdtime` with `clock_cpu_gettime`. - Removed redundant timer frequency definitions. - Added static assertions to check the value of `CPUTIME_TIMER_FREQ`. - Initialized `tick_cycles` based on `CPUTIME_TIMER_FREQ`. - Integrated `ktime` support for tick initialization. Signed-off-by: Shell <smokewood@qq.com> Reviewed-on: https://github.com/RT-Thread/rt-thread/pull/9164 Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-15 12:06:17 +08:00
help
Using the common64 implementation under ./libcpu/risc-v
endif
feat: support ARCH_REMAP_KERNEL on libcpu/c906 (#9123) feat: [libcpu/c906] support ARCH_REMAP_KERNEL This change was necessary to enable the remapping of the kernel image to a high virtual address region on the c906 platform. Changes: - Introduced new configuration options `ARCH_REMAP_KERNEL`, and `ARCH_USING_ASID` under the `ARCH_RISCV64` section. - Updated MMU initialization and switching functions to incorporate remapping handling. - Modified page table setup for proper memory attribute settings. - Added support for early memory setup, kernel remapping - Added conditional compilation for ASID support in the `rt_aspace` struct, since this is not enable currently for most architecture. Signed-off-by: Shell <smokewood@qq.com>
2024-07-11 11:00:04 +08:00
config ARCH_REMAP_KERNEL
bool
depends on RT_USING_SMART
help
Remapping kernel image to high virtual address region
config ARCH_USING_ASID
bool
depends on RT_USING_SMART
help
Using ASID support from architecture
[libcpu] rv64: support for ARCH_REMAP_KERNEL (#9067) * [libcpu] support for ARCH_REMAP_KERNEL These changes introduce support for the ARCH_REMAP_KERNEL configuration, which isolates kernel space in high virtual address regions. This feature is necessary to enhance memory protection and management by segregating user and kernel spaces more effectively. Changes: - Updated conditional macros to check for ARCH_REMAP_KERNEL instead of ARCH_KERNEL_IN_HIGH_VA in board initialization files to reflect the new configuration option. - Modified qemu-virt64-riscv Kconfig and SConstruct files to include and utilize ARCH_REMAP_KERNEL. - Created a new linker script `link_smart.lds` for smart linking in qemu-virt64-riscv. - Updated rtconfig.py to use a more flexible execution path setup. - Enhanced user address space definitions in `lwp_arch.h` to support the new virtual address mappings. - Adjusted kernel memory initialization and mapping logic in `c906/mmu.c` and `virt64/mmu.c` to account for high virtual address regions. - Added Kconfig option to enable ARCH_REMAP_KERNEL for RISCV64 architectures. - Enhanced memory setup functions to support new mapping scheme, including updates to early page table setup and address relocation logic. These modifications ensure that the system can utilize high memory addresses for the kernel, improving memory isolation and system stability. Signed-off-by: Shell <smokewood@qq.com> * fixup: CI run failed * bsp: default config without using smart * fixup: static checks * restore rt_hw_mmu_kernel_map_init for D1 --------- Signed-off-by: Shell <smokewood@qq.com>
2024-06-18 11:15:59 +08:00
Update Kconfig. 1. Add IPADDR/GWADDR etc; 2. Add Kconfig for libcpu.
2017-10-31 09:54:23 +08:00
config ARCH_IA32
bool
[bsp][tms320f28379d] Classify c28x into ti-dsp
2018-11-24 17:41:55 +08:00
config ARCH_TIDSP
[bsp][tms320f28379d] Add support of Kconfig
2018-11-18 12:06:52 +08:00
bool
[bsp][tms320f28379d] Classify c28x into ti-dsp
2018-11-24 17:41:55 +08:00
config ARCH_TIDSP_C28X
bool
select ARCH_TIDSP
[bsp][tms320f28379d] Add support of Kconfig
2018-11-18 12:06:52 +08:00
select ARCH_CPU_STACK_GROWS_UPWARD
Update Kconfig. 1. Add IPADDR/GWADDR etc; 2. Add Kconfig for libcpu.
2017-10-31 09:54:23 +08:00
config ARCH_HOST_SIMULATOR
bool
[Kernel] Add ARCH_CPU_STACK_GROWS_UPWARD option
2018-11-11 15:56:02 +08:00
config ARCH_CPU_STACK_GROWS_UPWARD
bool
default n
[arm64] add hw thread self (#8942) * [libcpu] arm64: Add hardware thread_self support This patch introduces hardware-based thread self-identification for the AArch64 architecture. It optimizes thread management by using hardware registers to store and access the current thread's pointer, reducing overhead and improving overall performance. Changes include: - Added `ARCH_USING_HW_THREAD_SELF` configuration option. - Modified `rtdef.h`, `rtsched.h` to conditionally include `critical_switch_flag` based on the new config. - Updated context management in `context_gcc.S`, `cpuport.h` to support hardware-based thread self. - Enhanced `scheduler_mp.c` and `thread.c` to leverage the new hardware thread self feature. These modifications ensure better scheduling and thread handling, particularly in multi-core environments, by minimizing the software overhead associated with thread management. Signed-off-by: Shell <smokewood@qq.com> * fixup: address suggestion * fixup: rt_current_thread as global * scheduler: add cpu object for UP scheduler Also, maintain the rt_current_thread in cpu object on UP scheduler. --------- Signed-off-by: Shell <smokewood@qq.com>
2024-05-28 14:27:55 +08:00
config ARCH_USING_HW_THREAD_SELF
bool
default n