98 lines
3.0 KiB
ArmAsm
98 lines
3.0 KiB
ArmAsm
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/*
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* Copyright (c) 2006-2020, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Date Author Notes
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* 2020-01-15 bigmagic the first version
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* 2020-08-10 SummerGift support clang compiler
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*/
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.section ".text.entrypoint","ax"
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.globl _start
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_start:
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/* Read cpu id */
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mrs x1, mpidr_el1
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and x1, x1, #3
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cbz x1, cpu_setup /* If cpu id > 0, stop slave cores */
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cpu_idle:
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wfe
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b cpu_idle
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cpu_setup:
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ldr x1, =_start
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mrs x0, CurrentEL /* CurrentEL Register. bit 2, 3. Others reserved */
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and x0, x0, #12 /* Clear reserved bits */
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/* Running at EL3? */
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cmp x0, #12 /* EL3 value is 0b1100 */
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bne cpu_not_in_el3
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/* Should never be executed, just for completeness. (EL3) */
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mov x0, #(1 << 0) /* EL0 and EL1 are in Non-Secure state */
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orr x0, x0, #(1 << 4) /* RES1 */
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orr x0, x0, #(1 << 5) /* RES1 */
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orr x0, x0, #(1 << 7) /* SMC instructions are undefined at EL1 and above */
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orr x0, x0, #(1 << 8) /* HVC instructions are enabled at EL1 and above */
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orr x0, x0, #(1 << 10) /* The next lower level is AArch64 */
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msr scr_el3, x2
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mov x2, #0x3c9
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msr spsr_el3, x2 /* 0b1111001001 */
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adr x2, cpu_not_in_el3
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msr elr_el3, x2
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eret /* Exception Return: from EL3, continue from cpu_not_in_el3 */
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cpu_not_in_el3: /* Running at EL2 or EL1 */
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cmp x0, #4 /* EL1 = 0100 */
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beq cpu_in_el1 /* Halt this core if running in El1 */
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cpu_in_el2:
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msr sp_el1, x1
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/* Enable CNTP for EL1 */
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mrs x0, cnthctl_el2 /* Counter-timer Hypervisor Control register */
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orr x0, x0, #3
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msr cnthctl_el2, x0
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msr cntvoff_el2, xzr
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mov x0, #(1 << 31) /* Enable AArch64 in EL1 */
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orr x0, x0, #(1 << 1) /* SWIO hardwired on Pi3 */
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msr hcr_el2, x0
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/* Change execution level to EL1 */
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mov x2, #0x3c4
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msr spsr_el2, x2 /* 0b1111000100 */
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adr x2, cpu_in_el1
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msr elr_el2, x2
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eret
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cpu_in_el1:
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mov sp, x1 /* Set sp in el1 */
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/* Avoid trap from SIMD or float point instruction */
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mov x1, #0x00300000 /* Don't trap any SIMD/FP instructions in both EL0 and EL1 */
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msr cpacr_el1, x1
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mrs x1, sctlr_el1
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orr x1, x1, #(1 << 12) /* Enable Instruction */
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bic x1, x1, #(3 << 3) /* Disable SP Alignment check */
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bic x1, x1, #(1 << 1) /* Disable Alignment check */
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msr sctlr_el1, x1
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ldr x1, =__bss_start
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ldr w2, =__bss_size
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clean_bss_loop:
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cbz w2, jump_to_entry
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str xzr, [x1], #8
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sub w2, w2, #1
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cbnz w2, clean_bss_loop
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jump_to_entry:
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b rtthread_startup
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b cpu_idle /* For failsafe, halt this core too */
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