644 lines
50 KiB
C
644 lines
50 KiB
C
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////////////////////////////////////////////////////////////////////////////////
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/// @file reg_common.h
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/// @author AE TEAM
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/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
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/// MM32 FIRMWARE LIBRARY.
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////////////////////////////////////////////////////////////////////////////////
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/// @attention
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///
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/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
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/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
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/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
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/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
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/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
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/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
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///
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/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
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////////////////////////////////////////////////////////////////////////////////
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// Define to prevent recursive inclusion
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#ifndef __REG_COMMON_H
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#define __REG_COMMON_H
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// Files includes
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#include <stdint.h>
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#include <stdbool.h>
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#include "types.h"
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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#ifndef HSE_STARTUP_TIMEOUT
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#define HSE_STARTUP_TIMEOUT (0x0500U) ///< Time out for HSE start up.
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#endif
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#ifdef CUSTOM_HSE_VAL
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#ifndef HSE_VALUE
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#define HSE_VALUE (12000000U) ///< Value of the External oscillator in Hz.
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#endif
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#else
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#ifndef HSE_VALUE
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#define HSE_VALUE (8000000U) ///< Value of the External oscillator in Hz.
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#endif
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#endif
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#define HSI_VALUE_PLL_ON (8000000U) ///< Value of the Internal oscillator in Hz.
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#define HSI_DIV6 (8000000U) ///< Value of the Internal oscillator in Hz.
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// Value of the Internal oscillator in Hz.
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#define LSI_VALUE (40000U) ///< Value of the Internal oscillator in Hz.
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#ifndef HSI_VALUE
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#define HSI_VALUE (8000000U) ///< Value of the Internal oscillator in Hz.
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#endif
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#define __MPU_PRESENT (0) ///< Cortex-M3 does not provide a MPU present or not
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#ifndef __NVIC_PRIO_BITS
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#define __NVIC_PRIO_BITS (4) ///< Cortex-M3 uses 4 Bits for the Priority Levels
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//#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
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#endif
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#define __Vendor_SysTickConfig (0) ///< Set to 1 if different SysTick Config is used
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////////////////////////////////////////////////////////////////////////////////
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/// @brief MM32 MCU Interrupt Handle
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////////////////////////////////////////////////////////////////////////////////
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typedef enum IRQn {
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NonMaskableInt_IRQn = -14, ///< 2 Non Maskable Interrupt
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MemoryManagement_IRQn = -12, ///< 4 Cortex-M3 Memory Management Interrupt
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BusFault_IRQn = -11, ///< 5 Cortex-M3 Bus Fault Interrupt
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UsageFault_IRQn = -10, ///< 6 Cortex-M3 Usage Fault Interrupt
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SVCall_IRQn = -5, ///< 11 Cortex-M3 SV Call Interrupt
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DebugMonitor_IRQn = -4, ///< 12 Cortex-M3 Debug Monitor Interrupt
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PendSV_IRQn = -2, ///< 14 Cortex-M3 Pend SV Interrupt
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SysTick_IRQn = -1, ///< 15 Cortex-M3 System Tick Interrupt
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WWDG_IWDG_IRQn = 0, ///< Watchdog interrupt
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WWDG_IRQn = 0, ///< Watchdog interrupt
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PVD_IRQn = 1, ///< (PVD) Interrupt
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TAMPER_IRQn = 2, ///< Intrusion detection interrupted
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RTC_IRQn = 3, ///< Real-time clock (RTC) global interrupt
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FLASH_IRQn = 4, ///< Flash global interrupt
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RCC_CRS_IRQn = 5, ///< RCC and CRS global interrupt
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EXTI0_IRQn = 6, ///< EXTI line 0 interrupt
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EXTI1_IRQn = 7, ///< EXTI line 1 interrupt
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EXTI2_IRQn = 8, ///< EXTI line 2 interrupt
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EXTI3_IRQn = 9, ///< EXTI line 3 interrupted
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EXTI4_IRQn = 10, ///< EXTI line 4 interrupt
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DMA1_Channel1_IRQn = 11, ///< DMA1 channel 1 global interrupt
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DMA1_Channel2_IRQn = 12, ///< DMA1 channel 2 global interrupt
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DMA1_Channel3_IRQn = 13, ///< DMA1 channel 3 global interrupt
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DMA1_Channel4_IRQn = 14, ///< DMA1 channel 4 global interrupt
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DMA1_Channel5_IRQn = 15, ///< DMA1 channel 5 global interrupt
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DMA1_Channel6_IRQn = 16, ///< DMA1 channel 6 global interrupt
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DMA1_Channel7_IRQn = 17, ///< DMA1 channel 7 global interrupt
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ADC1_IRQn = 18, ///< ADC1 global interrupt
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ADC1_2_IRQn = 18, ///< ADC1&ADC2 global interrupt
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ADC2_IRQn = 18, ///< ADC2 global interrupt
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FlashCache_IRQn = 19, ///< FlashCache outage
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CAN1_RX_IRQn = 21, ///< CAN1 receive interrupt
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CAN_IRQn = 21, ///< CAN interrupt
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EXTI9_5_IRQn = 23, ///< EXTI line [9: 5] interrupted
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TIM1_BRK_IRQn = 24, ///< TIM1 disconnect interrupt
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TIM1_UP_IRQn = 25, ///< TIM1 update interrupt
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IM1_TRG_COM_IRQn = 26, ///< TIM1 trigger and communication interrupt
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TIM1_CC_IRQn = 27, ///< TIM1 capture compare interrupt
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TIM2_IRQn = 28, ///< TIM2 global interrupt
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TIM3_IRQn = 29, ///< TIM3 global interrupt
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TIM4_IRQn = 30, ///< TIM4 global interrupt
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I2C1_IRQn = 31, ///< I2C1 global interrupt
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I2C2_IRQn = 33, ///< I2C2 global interrupt
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SPI1_IRQn = 35, ///< SPI1 global interrupt
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SPI2_IRQn = 36, ///< SPI2 global interrupt
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UART1_IRQn = 37, ///< UART1 global interrupt
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UART2_IRQn = 38, ///< UART2 global interrupt
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UART3_IRQn = 39, ///< UART3 global interrupt
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EXTI15_10_IRQn = 40, ///< EXTI line [15: 10] interrupted
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RTCAlarm_IRQn = 41, ///< RTC alarm connected to EXTI interrupted
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USB_WKUP_IRQn = 42, ///< Wake-up interrupt from USB connected to EXTI
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TIM8_BRK_IRQn = 43, ///< TIM8 brake interruption
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TIM8_UP_IRQn = 44, ///< TIM8 update interrupt
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TIM8_TRG_COM_IRQn = 45, ///< TIM8 trigger, communication interrupt
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TIM8_CC_IRQn = 46, ///< TIM8 capture compare interrupt
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ADC3_IRQn = 47, ///< ADC3 global interrupt
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SDIO_IRQn = 49, ///< SDIO global interrupt
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TIM5_IRQn = 50, ///< TIM5 global interrupt
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SPI3_IRQn = 51, ///< SPI3 global interrupt
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UART4_IRQn = 52, ///< UART4 global interrupt
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UART5_IRQn = 53, ///< UART5 global interrupt
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TIM6_IRQn = 54, ///< TIM6 global interrupt
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TIM7_IRQn = 55, ///< TIM7 global interrupt
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DMA2_Channel1_IRQn = 56, ///< DMA2 channel 1 global interrupt
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DMA2_Channel2_IRQn = 57, ///< DMA2 channel 2 global interrupt
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DMA2_Channel3_IRQn = 58, ///< DMA2 channel 3 global interrupt
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DMA2_Channel4_IRQn = 59, ///< DMA2 channel 4 global interrupt
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DMA2_Channel5_IRQn = 60, ///< DMA2 channel 5 global interrupt
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ETHERNET_MAC_IRQn = 61, ///< ETHERNET global interrupt
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COMP1_2_IRQn = 64, ///< Comparator 1/2 interrupt connected to EXTI
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USB_FS_IRQn = 67, ///< USB FS global interrupt
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UART6_IRQn = 71, ///< UART6 global interrupt
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UART7_IRQn = 82, ///< UART7 global interrupt
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UART8_IRQn = 83, ///< UART8 global interrupt
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} IRQn_Type;
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#include <core_cm3.h>
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#define PERIPH_BASE (0x40000000U) ///< Peripheral base address in the alias region
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#define EEPROM_BASE (0x08100000U) ///< EEPROM base address in the alias region
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#define SRAM_BITBAND_BASE (0x22000000U) ///< Peripheral base address in the bit-band region
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#define PERIPH_BITBAND_BASE (0x42000000U) ///< SRAM base address in the bit-band region
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#define APB1PERIPH_BASE (PERIPH_BASE + 0x00000000)
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#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
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#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
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#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
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#define AHB3PERIPH_BASE (PERIPH_BASE + 0x20000000)
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////////////////////////////////////////////////////////////////////////////////
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/// @brief UID type pointer Definition
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////////////////////////////////////////////////////////////////////////////////
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#define UID_BASE (0x1FFFF7E0U) ///< Unique device ID register base address
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///////////////////////////////////////////////////////////////////////////////
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/// @brief Nested Vectored Interrupt Controller
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///////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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/// @brief NVIC_ISER Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define NVIC_ISER_SETENA (0xFFFFFFFFU) ///< Interrupt set enable bits
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#define NVIC_ISER_SETENA_0 (0x00000001U) ///< bit 0
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#define NVIC_ISER_SETENA_1 (0x00000002U) ///< bit 1
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#define NVIC_ISER_SETENA_2 (0x00000004U) ///< bit 2
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#define NVIC_ISER_SETENA_3 (0x00000008U) ///< bit 3
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#define NVIC_ISER_SETENA_4 (0x00000010U) ///< bit 4
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#define NVIC_ISER_SETENA_5 (0x00000020U) ///< bit 5
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#define NVIC_ISER_SETENA_6 (0x00000040U) ///< bit 6
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#define NVIC_ISER_SETENA_7 (0x00000080U) ///< bit 7
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#define NVIC_ISER_SETENA_8 (0x00000100U) ///< bit 8
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#define NVIC_ISER_SETENA_9 (0x00000200U) ///< bit 9
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#define NVIC_ISER_SETENA_10 (0x00000400U) ///< bit 10
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#define NVIC_ISER_SETENA_11 (0x00000800U) ///< bit 11
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#define NVIC_ISER_SETENA_12 (0x00001000U) ///< bit 12
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#define NVIC_ISER_SETENA_13 (0x00002000U) ///< bit 13
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#define NVIC_ISER_SETENA_14 (0x00004000U) ///< bit 14
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#define NVIC_ISER_SETENA_15 (0x00008000U) ///< bit 15
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#define NVIC_ISER_SETENA_16 (0x00010000U) ///< bit 16
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#define NVIC_ISER_SETENA_17 (0x00020000U) ///< bit 17
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#define NVIC_ISER_SETENA_18 (0x00040000U) ///< bit 18
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#define NVIC_ISER_SETENA_19 (0x00080000U) ///< bit 19
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#define NVIC_ISER_SETENA_20 (0x00100000U) ///< bit 20
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#define NVIC_ISER_SETENA_21 (0x00200000U) ///< bit 21
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#define NVIC_ISER_SETENA_22 (0x00400000U) ///< bit 22
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#define NVIC_ISER_SETENA_23 (0x00800000U) ///< bit 23
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#define NVIC_ISER_SETENA_24 (0x01000000U) ///< bit 24
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#define NVIC_ISER_SETENA_25 (0x02000000U) ///< bit 25
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#define NVIC_ISER_SETENA_26 (0x04000000U) ///< bit 26
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#define NVIC_ISER_SETENA_27 (0x08000000U) ///< bit 27
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#define NVIC_ISER_SETENA_28 (0x10000000U) ///< bit 28
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#define NVIC_ISER_SETENA_29 (0x20000000U) ///< bit 29
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#define NVIC_ISER_SETENA_30 (0x40000000U) ///< bit 30
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#define NVIC_ISER_SETENA_31 (0x80000000U) ///< bit 31
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////////////////////////////////////////////////////////////////////////////////
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/// @brief NVIC_ICER Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define NVIC_ICER_CLRENA (0xFFFFFFFFU) ///< Interrupt clear-enable bits
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#define NVIC_ICER_CLRENA_0 (0x00000001U) ///< bit 0
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#define NVIC_ICER_CLRENA_1 (0x00000002U) ///< bit 1
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#define NVIC_ICER_CLRENA_2 (0x00000004U) ///< bit 2
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#define NVIC_ICER_CLRENA_3 (0x00000008U) ///< bit 3
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#define NVIC_ICER_CLRENA_4 (0x00000010U) ///< bit 4
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#define NVIC_ICER_CLRENA_5 (0x00000020U) ///< bit 5
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#define NVIC_ICER_CLRENA_6 (0x00000040U) ///< bit 6
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#define NVIC_ICER_CLRENA_7 (0x00000080U) ///< bit 7
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#define NVIC_ICER_CLRENA_8 (0x00000100U) ///< bit 8
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#define NVIC_ICER_CLRENA_9 (0x00000200U) ///< bit 9
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#define NVIC_ICER_CLRENA_10 (0x00000400U) ///< bit 10
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#define NVIC_ICER_CLRENA_11 (0x00000800U) ///< bit 11
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#define NVIC_ICER_CLRENA_12 (0x00001000U) ///< bit 12
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#define NVIC_ICER_CLRENA_13 (0x00002000U) ///< bit 13
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#define NVIC_ICER_CLRENA_14 (0x00004000U) ///< bit 14
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#define NVIC_ICER_CLRENA_15 (0x00008000U) ///< bit 15
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#define NVIC_ICER_CLRENA_16 (0x00010000U) ///< bit 16
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#define NVIC_ICER_CLRENA_17 (0x00020000U) ///< bit 17
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#define NVIC_ICER_CLRENA_18 (0x00040000U) ///< bit 18
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#define NVIC_ICER_CLRENA_19 (0x00080000U) ///< bit 19
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#define NVIC_ICER_CLRENA_20 (0x00100000U) ///< bit 20
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#define NVIC_ICER_CLRENA_21 (0x00200000U) ///< bit 21
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#define NVIC_ICER_CLRENA_22 (0x00400000U) ///< bit 22
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#define NVIC_ICER_CLRENA_23 (0x00800000U) ///< bit 23
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#define NVIC_ICER_CLRENA_24 (0x01000000U) ///< bit 24
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#define NVIC_ICER_CLRENA_25 (0x02000000U) ///< bit 25
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#define NVIC_ICER_CLRENA_26 (0x04000000U) ///< bit 26
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#define NVIC_ICER_CLRENA_27 (0x08000000U) ///< bit 27
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#define NVIC_ICER_CLRENA_28 (0x10000000U) ///< bit 28
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#define NVIC_ICER_CLRENA_29 (0x20000000U) ///< bit 29
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#define NVIC_ICER_CLRENA_30 (0x40000000U) ///< bit 30
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#define NVIC_ICER_CLRENA_31 (0x80000000U) ///< bit 31
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////////////////////////////////////////////////////////////////////////////////
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/// @brief NVIC_ISPR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define NVIC_ISPR_SETPEND (0xFFFFFFFFU) ///< Interrupt set-pending bits
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#define NVIC_ISPR_SETPEND_0 (0x00000001U) ///< bit 0
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#define NVIC_ISPR_SETPEND_1 (0x00000002U) ///< bit 1
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#define NVIC_ISPR_SETPEND_2 (0x00000004U) ///< bit 2
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#define NVIC_ISPR_SETPEND_3 (0x00000008U) ///< bit 3
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#define NVIC_ISPR_SETPEND_4 (0x00000010U) ///< bit 4
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#define NVIC_ISPR_SETPEND_5 (0x00000020U) ///< bit 5
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#define NVIC_ISPR_SETPEND_6 (0x00000040U) ///< bit 6
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#define NVIC_ISPR_SETPEND_7 (0x00000080U) ///< bit 7
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#define NVIC_ISPR_SETPEND_8 (0x00000100U) ///< bit 8
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#define NVIC_ISPR_SETPEND_9 (0x00000200U) ///< bit 9
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#define NVIC_ISPR_SETPEND_10 (0x00000400U) ///< bit 10
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#define NVIC_ISPR_SETPEND_11 (0x00000800U) ///< bit 11
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#define NVIC_ISPR_SETPEND_12 (0x00001000U) ///< bit 12
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#define NVIC_ISPR_SETPEND_13 (0x00002000U) ///< bit 13
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#define NVIC_ISPR_SETPEND_14 (0x00004000U) ///< bit 14
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#define NVIC_ISPR_SETPEND_15 (0x00008000U) ///< bit 15
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#define NVIC_ISPR_SETPEND_16 (0x00010000U) ///< bit 16
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#define NVIC_ISPR_SETPEND_17 (0x00020000U) ///< bit 17
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#define NVIC_ISPR_SETPEND_18 (0x00040000U) ///< bit 18
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#define NVIC_ISPR_SETPEND_19 (0x00080000U) ///< bit 19
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#define NVIC_ISPR_SETPEND_20 (0x00100000U) ///< bit 20
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#define NVIC_ISPR_SETPEND_21 (0x00200000U) ///< bit 21
|
||
|
|
#define NVIC_ISPR_SETPEND_22 (0x00400000U) ///< bit 22
|
||
|
|
#define NVIC_ISPR_SETPEND_23 (0x00800000U) ///< bit 23
|
||
|
|
#define NVIC_ISPR_SETPEND_24 (0x01000000U) ///< bit 24
|
||
|
|
#define NVIC_ISPR_SETPEND_25 (0x02000000U) ///< bit 25
|
||
|
|
#define NVIC_ISPR_SETPEND_26 (0x04000000U) ///< bit 26
|
||
|
|
#define NVIC_ISPR_SETPEND_27 (0x08000000U) ///< bit 27
|
||
|
|
#define NVIC_ISPR_SETPEND_28 (0x10000000U) ///< bit 28
|
||
|
|
#define NVIC_ISPR_SETPEND_29 (0x20000000U) ///< bit 29
|
||
|
|
#define NVIC_ISPR_SETPEND_30 (0x40000000U) ///< bit 30
|
||
|
|
#define NVIC_ISPR_SETPEND_31 (0x80000000U) ///< bit 31
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
/// @brief NVIC_ICPR Register Bit Definition
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
#define NVIC_ICPR_CLRPEND (0xFFFFFFFFU) ///< Interrupt clear-pending bits
|
||
|
|
#define NVIC_ICPR_CLRPEND_0 (0x00000001U) ///< bit 0
|
||
|
|
#define NVIC_ICPR_CLRPEND_1 (0x00000002U) ///< bit 1
|
||
|
|
#define NVIC_ICPR_CLRPEND_2 (0x00000004U) ///< bit 2
|
||
|
|
#define NVIC_ICPR_CLRPEND_3 (0x00000008U) ///< bit 3
|
||
|
|
#define NVIC_ICPR_CLRPEND_4 (0x00000010U) ///< bit 4
|
||
|
|
#define NVIC_ICPR_CLRPEND_5 (0x00000020U) ///< bit 5
|
||
|
|
#define NVIC_ICPR_CLRPEND_6 (0x00000040U) ///< bit 6
|
||
|
|
#define NVIC_ICPR_CLRPEND_7 (0x00000080U) ///< bit 7
|
||
|
|
#define NVIC_ICPR_CLRPEND_8 (0x00000100U) ///< bit 8
|
||
|
|
#define NVIC_ICPR_CLRPEND_9 (0x00000200U) ///< bit 9
|
||
|
|
#define NVIC_ICPR_CLRPEND_10 (0x00000400U) ///< bit 10
|
||
|
|
#define NVIC_ICPR_CLRPEND_11 (0x00000800U) ///< bit 11
|
||
|
|
#define NVIC_ICPR_CLRPEND_12 (0x00001000U) ///< bit 12
|
||
|
|
#define NVIC_ICPR_CLRPEND_13 (0x00002000U) ///< bit 13
|
||
|
|
#define NVIC_ICPR_CLRPEND_14 (0x00004000U) ///< bit 14
|
||
|
|
#define NVIC_ICPR_CLRPEND_15 (0x00008000U) ///< bit 15
|
||
|
|
#define NVIC_ICPR_CLRPEND_16 (0x00010000U) ///< bit 16
|
||
|
|
#define NVIC_ICPR_CLRPEND_17 (0x00020000U) ///< bit 17
|
||
|
|
#define NVIC_ICPR_CLRPEND_18 (0x00040000U) ///< bit 18
|
||
|
|
#define NVIC_ICPR_CLRPEND_19 (0x00080000U) ///< bit 19
|
||
|
|
#define NVIC_ICPR_CLRPEND_20 (0x00100000U) ///< bit 20
|
||
|
|
#define NVIC_ICPR_CLRPEND_21 (0x00200000U) ///< bit 21
|
||
|
|
#define NVIC_ICPR_CLRPEND_22 (0x00400000U) ///< bit 22
|
||
|
|
#define NVIC_ICPR_CLRPEND_23 (0x00800000U) ///< bit 23
|
||
|
|
#define NVIC_ICPR_CLRPEND_24 (0x01000000U) ///< bit 24
|
||
|
|
#define NVIC_ICPR_CLRPEND_25 (0x02000000U) ///< bit 25
|
||
|
|
#define NVIC_ICPR_CLRPEND_26 (0x04000000U) ///< bit 26
|
||
|
|
#define NVIC_ICPR_CLRPEND_27 (0x08000000U) ///< bit 27
|
||
|
|
#define NVIC_ICPR_CLRPEND_28 (0x10000000U) ///< bit 28
|
||
|
|
#define NVIC_ICPR_CLRPEND_29 (0x20000000U) ///< bit 29
|
||
|
|
#define NVIC_ICPR_CLRPEND_30 (0x40000000U) ///< bit 30
|
||
|
|
#define NVIC_ICPR_CLRPEND_31 (0x80000000U) ///< bit 31
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
/// @brief NVIC_IABR Register Bit Definition
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
#define NVIC_IABR_ACTIVE (0xFFFFFFFFU) ///< Interrupt active flags
|
||
|
|
#define NVIC_IABR_ACTIVE_0 (0x00000001U) ///< bit 0
|
||
|
|
#define NVIC_IABR_ACTIVE_1 (0x00000002U) ///< bit 1
|
||
|
|
#define NVIC_IABR_ACTIVE_2 (0x00000004U) ///< bit 2
|
||
|
|
#define NVIC_IABR_ACTIVE_3 (0x00000008U) ///< bit 3
|
||
|
|
#define NVIC_IABR_ACTIVE_4 (0x00000010U) ///< bit 4
|
||
|
|
#define NVIC_IABR_ACTIVE_5 (0x00000020U) ///< bit 5
|
||
|
|
#define NVIC_IABR_ACTIVE_6 (0x00000040U) ///< bit 6
|
||
|
|
#define NVIC_IABR_ACTIVE_7 (0x00000080U) ///< bit 7
|
||
|
|
#define NVIC_IABR_ACTIVE_8 (0x00000100U) ///< bit 8
|
||
|
|
#define NVIC_IABR_ACTIVE_9 (0x00000200U) ///< bit 9
|
||
|
|
#define NVIC_IABR_ACTIVE_10 (0x00000400U) ///< bit 10
|
||
|
|
#define NVIC_IABR_ACTIVE_11 (0x00000800U) ///< bit 11
|
||
|
|
#define NVIC_IABR_ACTIVE_12 (0x00001000U) ///< bit 12
|
||
|
|
#define NVIC_IABR_ACTIVE_13 (0x00002000U) ///< bit 13
|
||
|
|
#define NVIC_IABR_ACTIVE_14 (0x00004000U) ///< bit 14
|
||
|
|
#define NVIC_IABR_ACTIVE_15 (0x00008000U) ///< bit 15
|
||
|
|
#define NVIC_IABR_ACTIVE_16 (0x00010000U) ///< bit 16
|
||
|
|
#define NVIC_IABR_ACTIVE_17 (0x00020000U) ///< bit 17
|
||
|
|
#define NVIC_IABR_ACTIVE_18 (0x00040000U) ///< bit 18
|
||
|
|
#define NVIC_IABR_ACTIVE_19 (0x00080000U) ///< bit 19
|
||
|
|
#define NVIC_IABR_ACTIVE_20 (0x00100000U) ///< bit 20
|
||
|
|
#define NVIC_IABR_ACTIVE_21 (0x00200000U) ///< bit 21
|
||
|
|
#define NVIC_IABR_ACTIVE_22 (0x00400000U) ///< bit 22
|
||
|
|
#define NVIC_IABR_ACTIVE_23 (0x00800000U) ///< bit 23
|
||
|
|
#define NVIC_IABR_ACTIVE_24 (0x01000000U) ///< bit 24
|
||
|
|
#define NVIC_IABR_ACTIVE_25 (0x02000000U) ///< bit 25
|
||
|
|
#define NVIC_IABR_ACTIVE_26 (0x04000000U) ///< bit 26
|
||
|
|
#define NVIC_IABR_ACTIVE_27 (0x08000000U) ///< bit 27
|
||
|
|
#define NVIC_IABR_ACTIVE_28 (0x10000000U) ///< bit 28
|
||
|
|
#define NVIC_IABR_ACTIVE_29 (0x20000000U) ///< bit 29
|
||
|
|
#define NVIC_IABR_ACTIVE_30 (0x40000000U) ///< bit 30
|
||
|
|
#define NVIC_IABR_ACTIVE_31 (0x80000000U) ///< bit 31
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
/// @brief NVIC_PRI0 Register Bit Definition
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
#define NVIC_IPR0_PRI_0 (0x000000FFU) ///< Priority of interrupt 0
|
||
|
|
#define NVIC_IPR0_PRI_1 (0x0000FF00U) ///< Priority of interrupt 1
|
||
|
|
#define NVIC_IPR0_PRI_2 (0x00FF0000U) ///< Priority of interrupt 2
|
||
|
|
#define NVIC_IPR0_PRI_3 (0xFF000000U) ///< Priority of interrupt 3
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
/// @brief NVIC_PRI1 Register Bit Definition
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
#define NVIC_IPR1_PRI_4 (0x000000FFU) ///< Priority of interrupt 4
|
||
|
|
#define NVIC_IPR1_PRI_5 (0x0000FF00U) ///< Priority of interrupt 5
|
||
|
|
#define NVIC_IPR1_PRI_6 (0x00FF0000U) ///< Priority of interrupt 6
|
||
|
|
#define NVIC_IPR1_PRI_7 (0xFF000000U) ///< Priority of interrupt 7
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
/// @brief NVIC_PRI2 Register Bit Definition
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
#define NVIC_IPR2_PRI_8 (0x000000FFU) ///< Priority of interrupt 8
|
||
|
|
#define NVIC_IPR2_PRI_9 (0x0000FF00U) ///< Priority of interrupt 9
|
||
|
|
#define NVIC_IPR2_PRI_10 (0x00FF0000U) ///< Priority of interrupt 10
|
||
|
|
#define NVIC_IPR2_PRI_11 (0xFF000000U) ///< Priority of interrupt 11
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
/// @brief NVIC_PRI3 Register Bit Definition
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
#define NVIC_IPR3_PRI_12 (0x000000FFU) ///< Priority of interrupt 12
|
||
|
|
#define NVIC_IPR3_PRI_13 (0x0000FF00U) ///< Priority of interrupt 13
|
||
|
|
#define NVIC_IPR3_PRI_14 (0x00FF0000U) ///< Priority of interrupt 14
|
||
|
|
#define NVIC_IPR3_PRI_15 (0xFF000000U) ///< Priority of interrupt 15
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
/// @brief NVIC_PRI4 Register Bit Definition
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
#define NVIC_IPR4_PRI_16 (0x000000FFU) ///< Priority of interrupt 16
|
||
|
|
#define NVIC_IPR4_PRI_17 (0x0000FF00U) ///< Priority of interrupt 17
|
||
|
|
#define NVIC_IPR4_PRI_18 (0x00FF0000U) ///< Priority of interrupt 18
|
||
|
|
#define NVIC_IPR4_PRI_19 (0xFF000000U) ///< Priority of interrupt 19
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
/// @brief NVIC_PRI5 Register Bit Definition
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
#define NVIC_IPR5_PRI_20 (0x000000FFU) ///< Priority of interrupt 20
|
||
|
|
#define NVIC_IPR5_PRI_21 (0x0000FF00U) ///< Priority of interrupt 21
|
||
|
|
#define NVIC_IPR5_PRI_22 (0x00FF0000U) ///< Priority of interrupt 22
|
||
|
|
#define NVIC_IPR5_PRI_23 (0xFF000000U) ///< Priority of interrupt 23
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
/// @brief NVIC_PRI6 Register Bit Definition
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
#define NVIC_IPR6_PRI_24 (0x000000FFU) ///< Priority of interrupt 24
|
||
|
|
#define NVIC_IPR6_PRI_25 (0x0000FF00U) ///< Priority of interrupt 25
|
||
|
|
#define NVIC_IPR6_PRI_26 (0x00FF0000U) ///< Priority of interrupt 26
|
||
|
|
#define NVIC_IPR6_PRI_27 (0xFF000000U) ///< Priority of interrupt 27
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
/// @brief NVIC_PRI7 Register Bit Definition
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
#define NVIC_IPR7_PRI_28 (0x000000FFU) ///< Priority of interrupt 28
|
||
|
|
#define NVIC_IPR7_PRI_29 (0x0000FF00U) ///< Priority of interrupt 29
|
||
|
|
#define NVIC_IPR7_PRI_30 (0x00FF0000U) ///< Priority of interrupt 30
|
||
|
|
#define NVIC_IPR7_PRI_31 (0xFF000000U) ///< Priority of interrupt 31
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
/// @brief NVIC_PRI8 Register Bit Definition
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
#define NVIC_IPR7_PRI_32 (0x000000FFU) ///< Priority of interrupt 32
|
||
|
|
#define NVIC_IPR7_PRI_33 (0x0000FF00U) ///< Priority of interrupt 33
|
||
|
|
#define NVIC_IPR7_PRI_34 (0x00FF0000U) ///< Priority of interrupt 34
|
||
|
|
#define NVIC_IPR7_PRI_35 (0xFF000000U) ///< Priority of interrupt 35
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
/// @brief NVIC_PRI9 Register Bit Definition
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
#define NVIC_IPR7_PRI_36 (0x000000FFU) ///< Priority of interrupt 36
|
||
|
|
#define NVIC_IPR7_PRI_37 (0x0000FF00U) ///< Priority of interrupt 37
|
||
|
|
#define NVIC_IPR7_PRI_38 (0x00FF0000U) ///< Priority of interrupt 38
|
||
|
|
#define NVIC_IPR7_PRI_39 (0xFF000000U) ///< Priority of interrupt 39
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
/// @brief NVIC_PRI10 Register Bit Definition
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
#define NVIC_IPR7_PRI_40 (0x000000FFU) ///< Priority of interrupt 40
|
||
|
|
#define NVIC_IPR7_PRI_41 (0x0000FF00U) ///< Priority of interrupt 41
|
||
|
|
#define NVIC_IPR7_PRI_42 (0x00FF0000U) ///< Priority of interrupt 42
|
||
|
|
#define NVIC_IPR7_PRI_43 (0xFF000000U) ///< Priority of interrupt 43
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
/// @brief NVIC_PRI11 Register Bit Definition
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
#define NVIC_IPR7_PRI_44 (0x000000FFU) ///< Priority of interrupt 44
|
||
|
|
#define NVIC_IPR7_PRI_45 (0x0000FF00U) ///< Priority of interrupt 45
|
||
|
|
#define NVIC_IPR7_PRI_46 (0x00FF0000U) ///< Priority of interrupt 46
|
||
|
|
#define NVIC_IPR7_PRI_47 (0xFF000000U) ///< Priority of interrupt 47
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
/// @brief SCB_CPUID Register Bit Definition
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
#define SCB_CPUID_REVISION (0x0000000FU) ///< Implementation defined revision number
|
||
|
|
#define SCB_CPUID_PARTNO (0x0000FFF0U) ///< Number of processor within family
|
||
|
|
#define SCB_CPUID_Constant (0x000F0000U) ///< Reads as 0x0F
|
||
|
|
#define SCB_CPUID_VARIANT (0x00F00000U) ///< Implementation defined variant number
|
||
|
|
#define SCB_CPUID_IMPLEMENTER (0xFF000000U) ///< Implementer code. ARM is 0x41
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
/// @brief SCB_ICSR Register Bit Definition
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
#define SCB_ICSR_VECTACTIVE (0x000001FFU) ///< Active ISR number field
|
||
|
|
#define SCB_ICSR_RETTOBASE (0x00000800U) ///< All active exceptions minus the IPSR_current_exception yields the empty set
|
||
|
|
#define SCB_ICSR_VECTPENDING (0x003FF000U) ///< Pending ISR number field
|
||
|
|
#define SCB_ICSR_ISRPENDING (0x00400000U) ///< Interrupt pending flag
|
||
|
|
#define SCB_ICSR_ISRPREEMPT (0x00800000U) ///< It indicates that a pending interrupt becomes active in the next running cycle
|
||
|
|
#define SCB_ICSR_PENDSTCLR (0x02000000U) ///< Clear pending SysTick bit
|
||
|
|
#define SCB_ICSR_PENDSTSET (0x04000000U) ///< Set pending SysTick bit
|
||
|
|
#define SCB_ICSR_PENDSVCLR (0x08000000U) ///< Clear pending pendSV bit
|
||
|
|
#define SCB_ICSR_PENDSVSET (0x10000000U) ///< Set pending pendSV bit
|
||
|
|
#define SCB_ICSR_NMIPENDSET (0x80000000U) ///< Set pending NMI bit
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
/// @brief SCB_VTOR Register Bit Definition
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
#define SCB_VTOR_TBLOFF (0x1FFFFF80U) ///< Vector table base offset field
|
||
|
|
#define SCB_VTOR_TBLBASE (0x20000000U) ///< Table base in code(0) or RAM(1)
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
/// @brief SCB_AIRCR Register Bit Definition
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
#define SCB_AIRCR_VECTRESET (0x00000001U) ///< System Reset bit
|
||
|
|
#define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) ///< Clear active vector bit
|
||
|
|
#define SCB_AIRCR_SYSRESETREQ (0x00000004U) ///< Requests chip control logic to generate a reset
|
||
|
|
#define SCB_AIRCR_PRIGROUP (0x00000700U) ///< PRIGROUP[2:0] bits (Priority group)
|
||
|
|
#define SCB_AIRCR_PRIGROUP_0 (0x00000100U) ///< Bit 0
|
||
|
|
#define SCB_AIRCR_PRIGROUP_1 (0x00000200U) ///< Bit 1
|
||
|
|
#define SCB_AIRCR_PRIGROUP_2 (0x00000400U) ///< Bit 2
|
||
|
|
|
||
|
|
#define SCB_AIRCR_PRIGROUP0 (0x00000000U) ///< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority)
|
||
|
|
#define SCB_AIRCR_PRIGROUP1 (0x00000100U) ///< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority)
|
||
|
|
#define SCB_AIRCR_PRIGROUP2 (0x00000200U) ///< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority)
|
||
|
|
#define SCB_AIRCR_PRIGROUP3 (0x00000300U) ///< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority)
|
||
|
|
#define SCB_AIRCR_PRIGROUP4 (0x00000400U) ///< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority)
|
||
|
|
#define SCB_AIRCR_PRIGROUP5 (0x00000500U) ///< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority)
|
||
|
|
#define SCB_AIRCR_PRIGROUP6 (0x00000600U) ///< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority)
|
||
|
|
#define SCB_AIRCR_PRIGROUP7 (0x00000700U) ///< Priority group=7 (no pre-emption priority, 8 bits of subpriority)
|
||
|
|
|
||
|
|
#define SCB_AIRCR_ENDIANESS (0x00008000U) ///< Data endianness bit
|
||
|
|
#define SCB_AIRCR_VECTKEY (0xFFFF0000U) ///< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT)
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
/// @brief SCB_SCR Register Bit Definition
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
#define SCB_SCR_SLEEPONEXIT (0x02U) ///< Sleep on exit bit
|
||
|
|
#define SCB_SCR_SLEEPDEEP (0x04U) ///< Sleep deep bit
|
||
|
|
#define SCB_SCR_SEVONPEND (0x10U) ///< Wake up from WFE
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
/// @brief SCB_CCR Register Bit Definition
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
#define SCB_CCR_NONBASETHRDENA (0x0001U) ///< Thread mode can be entered from any level in Handler mode by controlled return value
|
||
|
|
#define SCB_CCR_USERSETMPEND (0x0002U) ///< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception
|
||
|
|
#define SCB_CCR_UNALIGN_TRP (0x0008U) ///< Trap for unaligned access
|
||
|
|
#define SCB_CCR_DIV_0_TRP (0x0010U) ///< Trap on Divide by 0
|
||
|
|
#define SCB_CCR_BFHFNMIGN (0x0100U) ///< Handlers running at priority -1 and -2
|
||
|
|
#define SCB_CCR_STKALIGN (0x0200U) ///< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
/// @brief SCB_SHPR Register Bit Definition
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
#define SCB_SHPR_PRI_N (0x000000FFU) ///< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor
|
||
|
|
#define SCB_SHPR_PRI_N1 (0x0000FF00U) ///< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved
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#define SCB_SHPR_PRI_N2 (0x00FF0000U) ///< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV
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#define SCB_SHPR_PRI_N3 (0xFF000000U) ///< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick
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////////////////////////////////////////////////////////////////////////////////
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/// @brief SCB_SHCSR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define SCB_SHCSR_MEMFAULTACT (0x00000001U) ///< MemManage is active
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#define SCB_SHCSR_BUSFAULTACT (0x00000002U) ///< BusFault is active
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#define SCB_SHCSR_USGFAULTACT (0x00000008U) ///< UsageFault is active
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#define SCB_SHCSR_SVCALLACT (0x00000080U) ///< SVCall is active
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#define SCB_SHCSR_MONITORACT (0x00000100U) ///< Monitor is active
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#define SCB_SHCSR_PENDSVACT (0x00000400U) ///< PendSV is active
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#define SCB_SHCSR_SYSTICKACT (0x00000800U) ///< SysTick is active
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#define SCB_SHCSR_USGFAULTPENDED (0x00001000U) ///< Usage Fault is pended
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#define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) ///< MemManage is pended
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#define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) ///< Bus Fault is pended
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#define SCB_SHCSR_SVCALLPENDED (0x00008000U) ///< SVCall is pended
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#define SCB_SHCSR_MEMFAULTENA (0x00010000U) ///< MemManage enable
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#define SCB_SHCSR_BUSFAULTENA (0x00020000U) ///< Bus Fault enable
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#define SCB_SHCSR_USGFAULTENA (0x00040000U) ///< UsageFault enable
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////////////////////////////////////////////////////////////////////////////////
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/// @brief SCB_CFSR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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///< MFSR
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#define SCB_CFSR_IACCVIOL (0x00000001U) ///< Instruction access violation
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#define SCB_CFSR_DACCVIOL (0x00000002U) ///< Data access violation
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#define SCB_CFSR_MUNSTKERR (0x00000008U) ///< Unstacking error
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#define SCB_CFSR_MSTKERR (0x00000010U) ///< Stacking error
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#define SCB_CFSR_MMARVALID (0x00000080U) ///< Memory Manage Address Register address valid flag
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///< BFSR
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#define SCB_CFSR_IBUSERR (0x00000100U) ///< Instruction bus error flag
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#define SCB_CFSR_PRECISERR (0x00000200U) ///< Precise data bus error
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#define SCB_CFSR_IMPRECISERR (0x00000400U) ///< Imprecise data bus error
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#define SCB_CFSR_UNSTKERR (0x00000800U) ///< Unstacking error
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#define SCB_CFSR_STKERR (0x00001000U) ///< Stacking error
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#define SCB_CFSR_BFARVALID (0x00008000U) ///< Bus Fault Address Register address valid flag
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///< UFSR
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#define SCB_CFSR_UNDEFINSTR (0x00010000U) ///< The processor attempt to excecute an undefined instruction
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#define SCB_CFSR_INVSTATE (0x00020000U) ///< Invalid combination of EPSR and instruction
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#define SCB_CFSR_INVPC (0x00040000U) ///< Attempt to load EXC_RETURN into pc illegally
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#define SCB_CFSR_NOCP (0x00080000U) ///< Attempt to use a coprocessor instruction
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#define SCB_CFSR_UNALIGNED (0x01000000U) ///< Fault occurs when there is an attempt to make an unaligned memory access
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#define SCB_CFSR_DIVBYZERO (0x02000000U) ///< Fault occurs when SDIV or DIV instruction is used with a divisor of 0
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////////////////////////////////////////////////////////////////////////////////
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/// @brief SCB_HFSR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define SCB_HFSR_VECTTBL (0x00000002U) ///< Fault occures because of vector table read on exception processing
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#define SCB_HFSR_FORCED (0x40000000U) ///< Hard Fault activated when a configurable Fault was received and cannot activate
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#define SCB_HFSR_DEBUGEVT (0x80000000U) ///< Fault related to debug
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////////////////////////////////////////////////////////////////////////////////
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/// @brief SCB_DFSR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define SCB_DFSR_HALTED (0x01U) ///< Halt request flag
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#define SCB_DFSR_BKPT (0x02U) ///< BKPT flag
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#define SCB_DFSR_DWTTRAP (0x04U) ///< Data Watchpoint and Trace (DWT) flag
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#define SCB_DFSR_VCATCH (0x08U) ///< Vector catch flag
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#define SCB_DFSR_EXTERNAL (0x10U) ///< External debug request flag
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////////////////////////////////////////////////////////////////////////////////
|
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/// @brief SCB_MMFAR Register Bit Definition
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
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|
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#define SCB_MMFAR_ADDRESS (0xFFFFFFFFU) ///< Mem Manage fault address field
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|
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////////////////////////////////////////////////////////////////////////////////
|
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|
|
/// @brief SCB_BFAR Register Bit Definition
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
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#define SCB_BFAR_ADDRESS (0xFFFFFFFFU) ///< Bus fault address field
|
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|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
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/// @brief SCB_AFSR Register Bit Definition
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
#define SCB_AFSR_IMPDEF (0xFFFFFFFFU) ///< Implementation defined
|
||
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|
||
|
|
#endif
|
||
|
|
/// @}
|
||
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|
||
|
|
/// @}
|
||
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|
||
|
|
/// @}
|
||
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|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
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|
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|