152 lines
8.3 KiB
C
152 lines
8.3 KiB
C
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//*****************************************************************************
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//
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// hw_memmap.h - Macros defining the memory map of the device.
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//
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// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
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//
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//*****************************************************************************
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#ifndef __HW_MEMMAP_H__
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#define __HW_MEMMAP_H__
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//*****************************************************************************
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//
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// The following are defines for the base address of the memories and
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// peripherals.
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//
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//*****************************************************************************
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#define FLASH_BASE 0x00000000 // FLASH memory
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#define SRAM_BASE 0x20000000 // SRAM memory
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#define WATCHDOG0_BASE 0x40000000 // Watchdog0
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#define WATCHDOG1_BASE 0x40001000 // Watchdog1
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#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A
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#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B
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#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C
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#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D
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#define SSI0_BASE 0x40008000 // SSI0
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#define SSI1_BASE 0x40009000 // SSI1
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#define SSI2_BASE 0x4000A000 // SSI2
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#define SSI3_BASE 0x4000B000 // SSI3
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#define UART0_BASE 0x4000C000 // UART0
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#define UART1_BASE 0x4000D000 // UART1
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#define UART2_BASE 0x4000E000 // UART2
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#define UART3_BASE 0x4000F000 // UART3
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#define UART4_BASE 0x40010000 // UART4
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#define UART5_BASE 0x40011000 // UART5
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#define UART6_BASE 0x40012000 // UART6
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#define UART7_BASE 0x40013000 // UART7
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#define I2C0_BASE 0x40020000 // I2C0
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#define I2C1_BASE 0x40021000 // I2C1
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#define I2C2_BASE 0x40022000 // I2C2
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#define I2C3_BASE 0x40023000 // I2C3
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#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E
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#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F
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#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G
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#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H
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#define PWM0_BASE 0x40028000 // Pulse Width Modulator (PWM)
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#define PWM1_BASE 0x40029000 // Pulse Width Modulator (PWM)
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#define QEI0_BASE 0x4002C000 // QEI0
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#define QEI1_BASE 0x4002D000 // QEI1
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#define TIMER0_BASE 0x40030000 // Timer0
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#define TIMER1_BASE 0x40031000 // Timer1
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#define TIMER2_BASE 0x40032000 // Timer2
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#define TIMER3_BASE 0x40033000 // Timer3
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#define TIMER4_BASE 0x40034000 // Timer4
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#define TIMER5_BASE 0x40035000 // Timer5
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#define WTIMER0_BASE 0x40036000 // Wide Timer0
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#define WTIMER1_BASE 0x40037000 // Wide Timer1
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#define ADC0_BASE 0x40038000 // ADC0
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#define ADC1_BASE 0x40039000 // ADC1
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#define COMP_BASE 0x4003C000 // Analog comparators
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#define GPIO_PORTJ_BASE 0x4003D000 // GPIO Port J
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#define CAN0_BASE 0x40040000 // CAN0
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#define CAN1_BASE 0x40041000 // CAN1
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#define WTIMER2_BASE 0x4004C000 // Wide Timer2
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#define WTIMER3_BASE 0x4004D000 // Wide Timer3
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#define WTIMER4_BASE 0x4004E000 // Wide Timer4
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#define WTIMER5_BASE 0x4004F000 // Wide Timer5
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#define USB0_BASE 0x40050000 // USB 0 Controller
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#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed)
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#define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed)
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#define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed)
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#define GPIO_PORTD_AHB_BASE 0x4005B000 // GPIO Port D (high speed)
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#define GPIO_PORTE_AHB_BASE 0x4005C000 // GPIO Port E (high speed)
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#define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed)
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#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed)
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#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed)
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#define GPIO_PORTJ_AHB_BASE 0x40060000 // GPIO Port J (high speed)
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#define GPIO_PORTK_BASE 0x40061000 // GPIO Port K
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#define GPIO_PORTL_BASE 0x40062000 // GPIO Port L
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#define GPIO_PORTM_BASE 0x40063000 // GPIO Port M
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#define GPIO_PORTN_BASE 0x40064000 // GPIO Port N
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#define GPIO_PORTP_BASE 0x40065000 // GPIO Port P
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#define GPIO_PORTQ_BASE 0x40066000 // GPIO Port Q
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#define GPIO_PORTR_BASE 0x40067000 // General-Purpose Input/Outputs
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// (GPIOs)
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#define GPIO_PORTS_BASE 0x40068000 // General-Purpose Input/Outputs
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// (GPIOs)
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#define GPIO_PORTT_BASE 0x40069000 // General-Purpose Input/Outputs
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// (GPIOs)
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#define EEPROM_BASE 0x400AF000 // EEPROM memory
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#define ONEWIRE0_BASE 0x400B6000 // 1-Wire Master Module
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#define I2C8_BASE 0x400B8000 // I2C8
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#define I2C9_BASE 0x400B9000 // I2C9
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#define I2C4_BASE 0x400C0000 // I2C4
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#define I2C5_BASE 0x400C1000 // I2C5
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#define I2C6_BASE 0x400C2000 // I2C6
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#define I2C7_BASE 0x400C3000 // I2C7
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#define EPI0_BASE 0x400D0000 // EPI0
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#define TIMER6_BASE 0x400E0000 // General-Purpose Timers
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#define TIMER7_BASE 0x400E1000 // General-Purpose Timers
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#define EMAC0_BASE 0x400EC000 // Ethernet Controller
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#define SYSEXC_BASE 0x400F9000 // System Exception Module
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#define HIB_BASE 0x400FC000 // Hibernation Module
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#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller
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#define SYSCTL_BASE 0x400FE000 // System Control
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#define UDMA_BASE 0x400FF000 // uDMA Controller
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#define CCM0_BASE 0x44030000 // Cyclical Redundancy Check (CRC)
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#define SHAMD5_BASE 0x44034000 // SHA/MD5 Accelerator
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#define AES_BASE 0x44036000 // Advance Encryption
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// Hardware-Accelerated Module
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#define DES_BASE 0x44038000 // Data Encryption Standard
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// Accelerator (DES)
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#define LCD0_BASE 0x44050000 // LCD Controller
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#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell
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#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace
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#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint
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#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl
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#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit
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#endif // __HW_MEMMAP_H__
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