2020-01-14 16:09:11 +08:00
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/*
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2021-01-04 15:22:50 +08:00
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* Copyright (c) 2006-2018, RT-Thread Development Team
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2020-01-14 16:09:11 +08:00
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*
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2021-01-04 15:22:50 +08:00
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-4-30 misonyo the first version.
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2020-01-14 16:09:11 +08:00
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*/
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#ifndef __DRV_SOUND_H_
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#define __DRV_SOUND_H_
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#include <rtthread.h>
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#include <rtdevice.h>
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#include <board.h>
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#include <rtdef.h>
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#include <rthw.h>
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#include "fsl_sai.h"
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#include "fsl_dmamux.h"
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#include "fsl_sai_edma.h"
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#define AUD_DMA_FIFO_SIZE (2048)
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2020-01-17 16:07:49 +08:00
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#define CODEC_I2C_NAME ("i2c1")
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2020-01-14 16:09:11 +08:00
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/* Select Audio/Video PLL (786.48 MHz) as sai1 clock source */
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#define DEMO_SAI1_CLOCK_SOURCE_SELECT (2U)
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/* Clock pre divider for sai1 clock source */
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#define DEMO_SAI1_CLOCK_SOURCE_PRE_DIVIDER (0U)
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/* Clock divider for sai1 clock source */
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#define DEMO_SAI1_CLOCK_SOURCE_DIVIDER (63U)
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/* Get frequency of sai1 clock */
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#define AUD_BLOCK_CNT 2
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#define AUD_BLOCK_SIZE 1024
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#define AUD_FIFO_SIZE (AUD_BLOCK_SIZE * AUD_BLOCK_CNT)
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#define DEMO_SAI_CLK_FREQ \
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(CLOCK_GetFreq(kCLOCK_AudioPllClk) / (DEMO_SAI1_CLOCK_SOURCE_DIVIDER + 1U) / \
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(DEMO_SAI1_CLOCK_SOURCE_PRE_DIVIDER + 1U))
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#define AUD_DMA_FIFO_SIZE (2048)
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struct saidma_tx_config
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{
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edma_handle_t edma;
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rt_uint8_t channel;
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dma_request_source_t request;
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sai_edma_handle_t txHandle;
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};
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struct saidma_rx_config
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{
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edma_handle_t edma;
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rt_uint8_t channel;
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dma_request_source_t request;
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sai_edma_handle_t rxHandle;
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};
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struct drv_sai {
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I2S_Type *base;
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IRQn_Type irqn;
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struct saidma_tx_config *dma_tx;
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struct saidma_rx_config *dma_rx;
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rt_uint8_t dma_flag;
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int txBlockIndex;
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int rxBlockIndex;
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};
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void sai_init(void);
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int rt_hw_sound_init(void);
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#endif
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