460 lines
15 KiB
C
460 lines
15 KiB
C
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//*****************************************************************************
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//
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// mpu.c - Driver for the Cortex-M3 memory protection unit (MPU).
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//
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// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! \addtogroup mpu_api
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//! @{
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//
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//*****************************************************************************
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#include <stdbool.h>
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#include <stdint.h>
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#include "inc/hw_ints.h"
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#include "inc/hw_nvic.h"
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#include "inc/hw_types.h"
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#include "driverlib/debug.h"
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#include "driverlib/interrupt.h"
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#include "driverlib/mpu.h"
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//*****************************************************************************
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//
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//! Enables and configures the MPU for use.
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//!
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//! \param ui32MPUConfig is the logical OR of the possible configurations.
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//!
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//! This function enables the Cortex-M memory protection unit. It also
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//! configures the default behavior when in privileged mode and while handling
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//! a hard fault or NMI. Prior to enabling the MPU, at least one region must
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//! be set by calling MPURegionSet() or else by enabling the default region for
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//! privileged mode by passing the \b MPU_CONFIG_PRIV_DEFAULT flag to
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//! MPUEnable(). Once the MPU is enabled, a memory management fault is
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//! generated for memory access violations.
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//!
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//! The \e ui32MPUConfig parameter should be the logical OR of any of the
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//! following:
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//!
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//! - \b MPU_CONFIG_PRIV_DEFAULT enables the default memory map when in
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//! privileged mode and when no other regions are defined. If this option
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//! is not enabled, then there must be at least one valid region already
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//! defined when the MPU is enabled.
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//! - \b MPU_CONFIG_HARDFLT_NMI enables the MPU while in a hard fault or NMI
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//! exception handler. If this option is not enabled, then the MPU is
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//! disabled while in one of these exception handlers and the default
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//! memory map is applied.
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//! - \b MPU_CONFIG_NONE chooses none of the above options. In this case,
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//! no default memory map is provided in privileged mode, and the MPU is not
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//! enabled in the fault handlers.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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MPUEnable(uint32_t ui32MPUConfig)
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{
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//
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// Check the arguments.
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//
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ASSERT(!(ui32MPUConfig & ~(MPU_CONFIG_PRIV_DEFAULT |
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MPU_CONFIG_HARDFLT_NMI)));
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//
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// Set the MPU control bits according to the flags passed by the user,
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// and also set the enable bit.
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//
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HWREG(NVIC_MPU_CTRL) = ui32MPUConfig | NVIC_MPU_CTRL_ENABLE;
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}
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//*****************************************************************************
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//
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//! Disables the MPU for use.
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//!
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//! This function disables the Cortex-M memory protection unit. When the
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//! MPU is disabled, the default memory map is used and memory management
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//! faults are not generated.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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MPUDisable(void)
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{
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//
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// Turn off the MPU enable bit.
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//
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HWREG(NVIC_MPU_CTRL) &= ~NVIC_MPU_CTRL_ENABLE;
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}
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//*****************************************************************************
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//
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//! Gets the count of regions supported by the MPU.
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//!
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//! This function is used to get the total number of regions that are supported
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//! by the MPU, including regions that are already programmed.
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//!
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//! \return The number of memory protection regions that are available
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//! for programming using MPURegionSet().
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//
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//*****************************************************************************
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uint32_t
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MPURegionCountGet(void)
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{
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//
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// Read the DREGION field of the MPU type register and mask off
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// the bits of interest to get the count of regions.
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//
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return((HWREG(NVIC_MPU_TYPE) & NVIC_MPU_TYPE_DREGION_M) >>
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NVIC_MPU_TYPE_DREGION_S);
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}
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//*****************************************************************************
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//
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//! Enables a specific region.
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//!
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//! \param ui32Region is the region number to enable.
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//!
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//! This function is used to enable a memory protection region. The region
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//! should already be configured with the MPURegionSet() function. Once
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//! enabled, the memory protection rules of the region are applied and access
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//! violations cause a memory management fault.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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MPURegionEnable(uint32_t ui32Region)
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{
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//
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// Check the arguments.
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//
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ASSERT(ui32Region < 8);
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//
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// Select the region to modify.
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//
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HWREG(NVIC_MPU_NUMBER) = ui32Region;
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//
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// Modify the enable bit in the region attributes.
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//
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HWREG(NVIC_MPU_ATTR) |= NVIC_MPU_ATTR_ENABLE;
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}
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//*****************************************************************************
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//
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//! Disables a specific region.
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//!
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//! \param ui32Region is the region number to disable.
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//!
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//! This function is used to disable a previously enabled memory protection
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//! region. The region remains configured if it is not overwritten with
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//! another call to MPURegionSet(), and can be enabled again by calling
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//! MPURegionEnable().
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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MPURegionDisable(uint32_t ui32Region)
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{
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//
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// Check the arguments.
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//
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ASSERT(ui32Region < 8);
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//
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// Select the region to modify.
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//
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HWREG(NVIC_MPU_NUMBER) = ui32Region;
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//
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// Modify the enable bit in the region attributes.
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//
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HWREG(NVIC_MPU_ATTR) &= ~NVIC_MPU_ATTR_ENABLE;
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}
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//*****************************************************************************
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//
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//! Sets up the access rules for a specific region.
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//!
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//! \param ui32Region is the region number to set up.
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//! \param ui32Addr is the base address of the region. It must be aligned
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//! according to the size of the region specified in ui32Flags.
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//! \param ui32Flags is a set of flags to define the attributes of the region.
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//!
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//! This function sets up the protection rules for a region. The region has
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//! a base address and a set of attributes including the size. The base
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//! address parameter, \e ui32Addr, must be aligned according to the size, and
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//! the size must be a power of 2.
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//!
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//! The \e ui32Flags parameter is the logical OR of all of the attributes
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//! of the region. It is a combination of choices for region size,
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//! execute permission, read/write permissions, disabled sub-regions,
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//! and a flag to determine if the region is enabled.
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//!
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//! The size flag determines the size of a region and must be one of the
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//! following:
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//!
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//! - \b MPU_RGN_SIZE_32B
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//! - \b MPU_RGN_SIZE_64B
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//! - \b MPU_RGN_SIZE_128B
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//! - \b MPU_RGN_SIZE_256B
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//! - \b MPU_RGN_SIZE_512B
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//! - \b MPU_RGN_SIZE_1K
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//! - \b MPU_RGN_SIZE_2K
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//! - \b MPU_RGN_SIZE_4K
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//! - \b MPU_RGN_SIZE_8K
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//! - \b MPU_RGN_SIZE_16K
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//! - \b MPU_RGN_SIZE_32K
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//! - \b MPU_RGN_SIZE_64K
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//! - \b MPU_RGN_SIZE_128K
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//! - \b MPU_RGN_SIZE_256K
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//! - \b MPU_RGN_SIZE_512K
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//! - \b MPU_RGN_SIZE_1M
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//! - \b MPU_RGN_SIZE_2M
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//! - \b MPU_RGN_SIZE_4M
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//! - \b MPU_RGN_SIZE_8M
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//! - \b MPU_RGN_SIZE_16M
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//! - \b MPU_RGN_SIZE_32M
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//! - \b MPU_RGN_SIZE_64M
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//! - \b MPU_RGN_SIZE_128M
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//! - \b MPU_RGN_SIZE_256M
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//! - \b MPU_RGN_SIZE_512M
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//! - \b MPU_RGN_SIZE_1G
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//! - \b MPU_RGN_SIZE_2G
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//! - \b MPU_RGN_SIZE_4G
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//!
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//! The execute permission flag must be one of the following:
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//!
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//! - \b MPU_RGN_PERM_EXEC enables the region for execution of code
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//! - \b MPU_RGN_PERM_NOEXEC disables the region for execution of code
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//!
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//! The read/write access permissions are applied separately for the
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//! privileged and user modes. The read/write access flags must be one
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//! of the following:
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//!
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//! - \b MPU_RGN_PERM_PRV_NO_USR_NO - no access in privileged or user mode
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//! - \b MPU_RGN_PERM_PRV_RW_USR_NO - privileged read/write, user no access
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//! - \b MPU_RGN_PERM_PRV_RW_USR_RO - privileged read/write, user read-only
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//! - \b MPU_RGN_PERM_PRV_RW_USR_RW - privileged read/write, user read/write
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//! - \b MPU_RGN_PERM_PRV_RO_USR_NO - privileged read-only, user no access
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//! - \b MPU_RGN_PERM_PRV_RO_USR_RO - privileged read-only, user read-only
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//!
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//! The region is automatically divided into 8 equally-sized sub-regions by
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//! the MPU. Sub-regions can only be used in regions of size 256 bytes
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//! or larger. Any of these 8 sub-regions can be disabled, allowing for
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//! creation of ``holes'' in a region which can be left open, or overlaid
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//! by another region with different attributes. Any of the 8 sub-regions
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//! can be disabled with a logical OR of any of the following flags:
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//!
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//! - \b MPU_SUB_RGN_DISABLE_0
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//! - \b MPU_SUB_RGN_DISABLE_1
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//! - \b MPU_SUB_RGN_DISABLE_2
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//! - \b MPU_SUB_RGN_DISABLE_3
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//! - \b MPU_SUB_RGN_DISABLE_4
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//! - \b MPU_SUB_RGN_DISABLE_5
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//! - \b MPU_SUB_RGN_DISABLE_6
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//! - \b MPU_SUB_RGN_DISABLE_7
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//!
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//! Finally, the region can be initially enabled or disabled with one of
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//! the following flags:
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//!
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//! - \b MPU_RGN_ENABLE
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//! - \b MPU_RGN_DISABLE
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//!
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//! As an example, to set a region with the following attributes: size of
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//! 32 KB, execution enabled, read-only for both privileged and user, one
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//! sub-region disabled, and initially enabled; the \e ui32Flags parameter
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//! would have the following value:
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//!
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//! <code>
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//! (MPU_RGN_SIZE_32K | MPU_RGN_PERM_EXEC | MPU_RGN_PERM_PRV_RO_USR_RO |
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//! MPU_SUB_RGN_DISABLE_2 | MPU_RGN_ENABLE)
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//! </code>
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//!
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//! \note This function writes to multiple registers and is not protected
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//! from interrupts. It is possible that an interrupt which accesses a
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//! region may occur while that region is in the process of being changed.
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//! The safest way to handle this is to disable a region before changing it.
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//! Refer to the discussion of this in the API Detailed Description section.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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MPURegionSet(uint32_t ui32Region, uint32_t ui32Addr, uint32_t ui32Flags)
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{
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//
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// Check the arguments.
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//
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ASSERT(ui32Region < 8);
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ASSERT(ui32Addr ==
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(ui32Addr & ~0 << (((ui32Flags & NVIC_MPU_ATTR_SIZE_M) >> 1) + 1)));
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//
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// Program the base address, use the region field to select the
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// region at the same time.
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//
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HWREG(NVIC_MPU_BASE) = ui32Addr | ui32Region | NVIC_MPU_BASE_VALID;
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//
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// Program the region attributes. Set the TEX field and the S, C,
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// and B bits to fixed values that are suitable for all Tiva C and
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// E Series memory.
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//
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HWREG(NVIC_MPU_ATTR) = ((ui32Flags & ~(NVIC_MPU_ATTR_TEX_M |
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NVIC_MPU_ATTR_CACHEABLE)) |
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NVIC_MPU_ATTR_SHAREABLE | NVIC_MPU_ATTR_BUFFRABLE);
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}
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//*****************************************************************************
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//
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//! Gets the current settings for a specific region.
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//!
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//! \param ui32Region is the region number to get.
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//! \param pui32Addr points to storage for the base address of the region.
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//! \param pui32Flags points to the attribute flags for the region.
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//!
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//! This function retrieves the configuration of a specific region. The
|
||
|
|
//! meanings and format of the parameters is the same as that of the
|
||
|
|
//! MPURegionSet() function.
|
||
|
|
//!
|
||
|
|
//! This function can be used to save the configuration of a region for later
|
||
|
|
//! use with the MPURegionSet() function. The region's enable state is
|
||
|
|
//! preserved in the attributes that are saved.
|
||
|
|
//!
|
||
|
|
//! \return None.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
void
|
||
|
|
MPURegionGet(uint32_t ui32Region, uint32_t *pui32Addr, uint32_t *pui32Flags)
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// Check the arguments.
|
||
|
|
//
|
||
|
|
ASSERT(ui32Region < 8);
|
||
|
|
ASSERT(pui32Addr);
|
||
|
|
ASSERT(pui32Flags);
|
||
|
|
|
||
|
|
//
|
||
|
|
// Select the region to get.
|
||
|
|
//
|
||
|
|
HWREG(NVIC_MPU_NUMBER) = ui32Region;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Read and store the base address for the region.
|
||
|
|
//
|
||
|
|
*pui32Addr = HWREG(NVIC_MPU_BASE) & NVIC_MPU_BASE_ADDR_M;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Read and store the region attributes.
|
||
|
|
//
|
||
|
|
*pui32Flags = HWREG(NVIC_MPU_ATTR);
|
||
|
|
}
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
//! Registers an interrupt handler for the memory management fault.
|
||
|
|
//!
|
||
|
|
//! \param pfnHandler is a pointer to the function to be called when the
|
||
|
|
//! memory management fault occurs.
|
||
|
|
//!
|
||
|
|
//! This function sets and enables the handler to be called when the MPU
|
||
|
|
//! generates a memory management fault due to a protection region access
|
||
|
|
//! violation.
|
||
|
|
//!
|
||
|
|
//! \sa IntRegister() for important information about registering interrupt
|
||
|
|
//! handlers.
|
||
|
|
//!
|
||
|
|
//! \return None.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
void
|
||
|
|
MPUIntRegister(void (*pfnHandler)(void))
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// Check the arguments.
|
||
|
|
//
|
||
|
|
ASSERT(pfnHandler);
|
||
|
|
|
||
|
|
//
|
||
|
|
// Register the interrupt handler.
|
||
|
|
//
|
||
|
|
IntRegister(FAULT_MPU, pfnHandler);
|
||
|
|
|
||
|
|
//
|
||
|
|
// Enable the memory management fault.
|
||
|
|
//
|
||
|
|
IntEnable(FAULT_MPU);
|
||
|
|
}
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
//! Unregisters an interrupt handler for the memory management fault.
|
||
|
|
//!
|
||
|
|
//! This function disables and clears the handler to be called when a
|
||
|
|
//! memory management fault occurs.
|
||
|
|
//!
|
||
|
|
//! \sa IntRegister() for important information about registering interrupt
|
||
|
|
//! handlers.
|
||
|
|
//!
|
||
|
|
//! \return None.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
void
|
||
|
|
MPUIntUnregister(void)
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// Disable the interrupt.
|
||
|
|
//
|
||
|
|
IntDisable(FAULT_MPU);
|
||
|
|
|
||
|
|
//
|
||
|
|
// Unregister the interrupt handler.
|
||
|
|
//
|
||
|
|
IntUnregister(FAULT_MPU);
|
||
|
|
}
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// Close the Doxygen group.
|
||
|
|
//! @}
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|