275 lines
8.6 KiB
C
275 lines
8.6 KiB
C
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/*
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* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-02-24 CDT first version
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*/
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include <rtthread.h>
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#if defined(BSP_USING_EXMC)
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#if defined(BSP_USING_SDRAM)
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#include "drv_sdram.h"
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#include "board_config.h"
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#include "sdram_port.h"
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/*******************************************************************************
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* Local type definitions ('typedef')
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******************************************************************************/
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/*******************************************************************************
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* Local pre-processor symbols/macros ('#define')
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******************************************************************************/
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//#define DRV_DEBUG
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#define LOG_TAG "drv.sdram"
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#include <drv_log.h>
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/*******************************************************************************
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* Global variable definitions (declared in header file with 'extern')
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******************************************************************************/
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#if defined (BSP_USING_SDRAM)
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rt_err_t rt_hw_board_sdram_init(void);
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#endif
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/*******************************************************************************
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* Local function prototypes ('static')
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******************************************************************************/
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/*******************************************************************************
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* Local variable definitions ('static')
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******************************************************************************/
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#ifdef RT_USING_MEMHEAP_AS_HEAP
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static struct rt_memheap _system_heap;
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#endif
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/*******************************************************************************
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* Function implementation - global ('extern') and local ('static')
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******************************************************************************/
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/**
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* @brief SDRAM initialization sequence.
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* @param [in] chip The command chip number.
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* @param [in] md_reg_value The SDRAM mode register value
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* @retval None
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*/
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static void _sdram_initialization_sequence(rt_uint32_t chip, rt_uint32_t md_reg_value)
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{
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/* SDRAM initialization sequence:
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CMD NOP->PrechargeAll->AutoRefresh->AutoRefresh->MdRegConfig->NOP */
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(void)EXMC_DMC_SetCommand(chip, 0UL, EXMC_DMC_CMD_NOP, 0UL);
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(void)EXMC_DMC_SetCommand(chip, 0UL, EXMC_DMC_CMD_PRECHARGE_ALL, 0UL);
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(void)EXMC_DMC_SetCommand(chip, 0UL, EXMC_DMC_CMD_AUTO_REFRESH, 0UL);
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(void)EXMC_DMC_SetCommand(chip, 0UL, EXMC_DMC_CMD_AUTO_REFRESH, 0UL);
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(void)EXMC_DMC_SetCommand(chip, 0UL, EXMC_DMC_CMD_MDREG_CONFIG, md_reg_value);
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(void)EXMC_DMC_SetCommand(chip, 0UL, EXMC_DMC_CMD_NOP, 0UL);
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}
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/**
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* @brief verify clock frequency.
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* @retval result
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*/
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static rt_int32_t _sdram_verify_clock_frequency(void)
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{
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rt_int32_t ret = RT_EOK;
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#if defined (HC32F4A0)
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/* EXCLK max frequency for SDRAM: 60MHz */
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if (CLK_GetBusClockFreq(CLK_BUS_EXCLK) > (60 * 1000000))
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{
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ret = -RT_ERROR;
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}
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#endif
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return ret;
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}
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/**
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* @brief SDRAM initialization.
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* @param None
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* @retval result
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*/
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static rt_int32_t _sdram_init(void)
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{
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rt_uint32_t md_reg_value;
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stc_exmc_dmc_init_t stcDmcInit;
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stc_exmc_dmc_chip_config_t stcCsConfig;
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/* verify SDRAM clock frequency */
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if (_sdram_verify_clock_frequency() != RT_EOK)
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{
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LOG_E("EXMC clock frequency is over limit for SDRAM!");
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return -RT_ERROR;
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}
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/* initialization SDRAM port.*/
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rt_hw_board_sdram_init();
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/* enable DMC clock */
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FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_DMC, ENABLE);
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/* enable DMC. */
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EXMC_DMC_Cmd(ENABLE);
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/* configure DMC width && refresh period & chip & timing. */
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(void)EXMC_DMC_StructInit(&stcDmcInit);
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stcDmcInit.u32RefreshPeriod = SDRAM_REFRESH_COUNT;
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stcDmcInit.u32ColumnBitsNumber = SDRAM_COLUMN_BITS;
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stcDmcInit.u32RowBitsNumber = SDRAM_ROW_BITS;
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stcDmcInit.u32MemBurst = SDRAM_BURST_LENGTH;
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stcDmcInit.u32AutoRefreshChips = EXMC_DMC_AUTO_REFRESH_4CHIPS;
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stcDmcInit.stcTimingConfig.u8CASL = SDRAM_CAS_LATENCY;
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stcDmcInit.stcTimingConfig.u8DQSS = 0U;
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stcDmcInit.stcTimingConfig.u8MRD = SDRAM_TMDR;
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stcDmcInit.stcTimingConfig.u8RAS = SDRAM_TRAS;
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stcDmcInit.stcTimingConfig.u8RC = SDRAM_TRC;
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stcDmcInit.stcTimingConfig.u8RCD_B = SDRAM_TRCD;
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stcDmcInit.stcTimingConfig.u8RCD_P = 0U;
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stcDmcInit.stcTimingConfig.u8RFC_B = SDRAM_TRFC;
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stcDmcInit.stcTimingConfig.u8RFC_P = 0U;
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stcDmcInit.stcTimingConfig.u8RP_B = SDRAM_TRP;
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stcDmcInit.stcTimingConfig.u8RP_P = 0U;
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stcDmcInit.stcTimingConfig.u8RRD = SDRAM_TRRD;
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stcDmcInit.stcTimingConfig.u8WR = SDRAM_TWR;
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stcDmcInit.stcTimingConfig.u8WTR = SDRAM_TWTR;
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stcDmcInit.stcTimingConfig.u8XP = SDRAM_TXP;
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stcDmcInit.stcTimingConfig.u8XSR = SDRAM_TXSR;
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stcDmcInit.stcTimingConfig.u8ESR = SDRAM_TESR;
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(void)EXMC_DMC_Init(&stcDmcInit);
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/* configure DMC address space. */
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stcCsConfig.u32AddrMatch = (SDRAM_BANK_ADDR >> 24);
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stcCsConfig.u32AddrMask = EXMC_DMC_ADDR_MASK_128MB;
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stcCsConfig.u32AddrDecodeMode = EXMC_DMC_CS_DECODE_ROWBANKCOL;
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(void)EXMC_DMC_ChipConfig(SDRAM_CHIP, &stcCsConfig);
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/* SDRAM initialization sequence. */
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md_reg_value = (SDRAM_MODEREG_BURST_TYPE | SDRAM_MODEREG_WRITEBURST_MODE | SDRAM_MODEREG_OPERATING_MODE);
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if (2U == stcDmcInit.stcTimingConfig.u8CASL)
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{
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md_reg_value |= SDRAM_MODEREG_CAS_LATENCY_2;
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}
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else
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{
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md_reg_value |= SDRAM_MODEREG_CAS_LATENCY_3;
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}
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if (EXMC_DMC_BURST_1BEAT == stcDmcInit.u32MemBurst)
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{
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md_reg_value |= SDRAM_MODEREG_BURST_LENGTH_1;
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}
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else if (EXMC_DMC_BURST_2BEAT == stcDmcInit.u32MemBurst)
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{
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md_reg_value |= SDRAM_MODEREG_BURST_LENGTH_2;
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}
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else if (EXMC_DMC_BURST_4BEAT == stcDmcInit.u32MemBurst)
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{
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md_reg_value |= SDRAM_MODEREG_BURST_LENGTH_4;
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}
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else
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{
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md_reg_value |= SDRAM_MODEREG_BURST_LENGTH_8;
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}
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_sdram_initialization_sequence(SDRAM_CHIP, md_reg_value);
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/* switch state from configure to ready */
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EXMC_DMC_SetState(EXMC_DMC_CTRL_STATE_GO);
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EXMC_DMC_SetState(EXMC_DMC_CTRL_STATE_WAKEUP);
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EXMC_DMC_SetState(EXMC_DMC_CTRL_STATE_GO);
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return RT_EOK;
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}
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int rt_hw_sdram_init(void)
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{
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rt_int32_t ret;
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ret = _sdram_init();
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if (RT_EOK != ret)
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{
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LOG_E("SDRAM init failed!");
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return -RT_ERROR;
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}
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#ifdef RT_USING_MEMHEAP_AS_HEAP
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/* If RT_USING_MEMHEAP_AS_HEAP is enabled, SDRAM is initialized to the heap */
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rt_memheap_init(&_system_heap, "sdram", (void *)SDRAM_BANK_ADDR, SDRAM_SIZE);
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#endif
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return ret;
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}
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INIT_BOARD_EXPORT(rt_hw_sdram_init);
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#ifdef DRV_DEBUG
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#ifdef FINSH_USING_MSH
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static int _sdram_test(void)
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{
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rt_uint32_t i;
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rt_uint32_t start_time;
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rt_uint32_t time_cast;
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#if SDRAM_DATA_WIDTH == EXMC_DMC_MEMORY_WIDTH_16BIT
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const char data_width = 2;
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rt_uint16_t data = 0;
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#else
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char data_width = 4;
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rt_uint32_t data = 0;
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#endif
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/* write data */
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LOG_D("writing the %ld bytes data, waiting....", SDRAM_SIZE);
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start_time = rt_tick_get();
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for (i = 0; i < SDRAM_SIZE / data_width; i++)
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{
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#if SDRAM_DATA_WIDTH == EXMC_DMC_MEMORY_WIDTH_16BIT
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*(__IO uint16_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint16_t)(i % 1000);
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#else
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*(__IO uint32_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint32_t)(i % 1000);
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#endif
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}
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time_cast = rt_tick_get() - start_time;
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LOG_D("write data success, total time: %d.%03dS.", time_cast / RT_TICK_PER_SECOND,
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time_cast % RT_TICK_PER_SECOND / ((RT_TICK_PER_SECOND * 1 + 999) / 1000));
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/* read data */
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LOG_D("start reading and verifying data, waiting....");
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for (i = 0; i < SDRAM_SIZE / data_width; i++)
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{
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#if SDRAM_DATA_WIDTH == EXMC_DMC_MEMORY_WIDTH_16BIT
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data = *(__IO uint16_t *)(SDRAM_BANK_ADDR + i * data_width);
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if (data != i % 1000)
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{
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LOG_E("SDRAM test failed!");
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break;
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}
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#else
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data = *(__IO uint32_t *)(SDRAM_BANK_ADDR + i * data_width);
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if (data != i % 1000)
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{
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LOG_E("SDRAM test failed!");
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break;
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}
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#endif
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}
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if (i >= SDRAM_SIZE / data_width)
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{
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LOG_D("SDRAM test success!");
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}
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return RT_EOK;
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}
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MSH_CMD_EXPORT(_sdram_test, sdram test)
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#endif /* FINSH_USING_MSH */
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#endif /* DRV_DEBUG */
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#endif /* BSP_USING_SDRAM */
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#endif /* BSP_USING_EXMC */
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