135 lines
3.3 KiB
C
135 lines
3.3 KiB
C
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/**************************************************************************//**
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*
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* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-3-4 CHChen First version
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*
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******************************************************************************/
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#include <rtconfig.h>
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#if defined(BSP_USING_CRC)
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#include <string.h>
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#include <rtdevice.h>
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#include <rtdbg.h>
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#include "NuMicro.h"
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#include "drv_pdma.h"
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/* Private define ---------------------------------------------------------------*/
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#define NU_CRYPTO_CRC_NAME "nu_CRC"
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/* Private variables ------------------------------------------------------------*/
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static struct rt_mutex s_CRC_mutex;
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static rt_uint32_t nu_crc_run(
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uint32_t u32OpMode,
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uint32_t u32Seed,
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uint32_t u32Attr,
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uint8_t *pu8InData,
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uint32_t u32DataLen
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)
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{
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uint32_t u32CalChecksum = 0;
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uint32_t i = 0;
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rt_mutex_take(&s_CRC_mutex, RT_WAITING_FOREVER);
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/* Configure CRC controller */
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CRC_Open(u32OpMode, u32Attr, u32Seed, CRC_CPU_WDATA_8);
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uint8_t *pu8InTempData = pu8InData;
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while (i < u32DataLen)
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{
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if (((((uint32_t)pu8InTempData) % 4) != 0) || (u32DataLen - i < 4))
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{
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CRC->CTL &= ~CRC_CTL_DATLEN_Msk;
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CRC_WRITE_DATA((*pu8InTempData) & 0xFF);
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pu8InTempData ++;
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i++;
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}
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else
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{
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CRC->CTL &= ~CRC_CTL_DATLEN_Msk;
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CRC->CTL |= CRC_CPU_WDATA_32;
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#if defined (NU_CRC_USE_PDMA)
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int32_t i32PDMATransCnt = (u32DataLen - i) / 4 ;
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i32PDMATransCnt = nu_pdma_mempush((void *)&CRC->DAT, pu8InTempData, 32, i32PDMATransCnt);
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if (i32PDMATransCnt > 0)
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{
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pu8InTempData += (i32PDMATransCnt * 4);
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i += (i32PDMATransCnt * 4);
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}
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#else
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CRC_WRITE_DATA(*(uint32_t *)pu8InTempData);
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pu8InTempData += 4;
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i += 4;
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#endif
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}
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}
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/* Get checksum value */
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u32CalChecksum = CRC_GetChecksum();
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rt_mutex_release(&s_CRC_mutex);
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return u32CalChecksum;
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}
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rt_err_t nu_crc_init(void)
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{
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SYS_ResetModule(CRC_RST);
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rt_mutex_init(&s_CRC_mutex, NU_CRYPTO_CRC_NAME, RT_IPC_FLAG_FIFO);
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return RT_EOK;
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}
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rt_uint32_t nu_crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, rt_size_t length)
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{
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uint32_t u32OpMode;
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uint32_t u32CRCAttr = 0;
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rt_uint32_t crc_result = 0;
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//select CRC operation mode
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switch (ctx->crc_cfg.poly)
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{
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case 0x04C11DB7:
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u32OpMode = CRC_32;
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break;
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case 0x00001021:
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u32OpMode = CRC_CCITT;
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break;
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case 0x00008005:
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u32OpMode = CRC_16;
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break;
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case 0x00000007:
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u32OpMode = CRC_8;
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break;
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default:
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return 0;
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}
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u32CRCAttr |= ctx->crc_cfg.flags & CRC_FLAG_REFOUT ? CRC_CHECKSUM_RVS : 0; //CRC Checksum Reverse
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u32CRCAttr |= ctx->crc_cfg.flags & CRC_FLAG_REFIN ? CRC_WDATA_RVS : 0; //CRC Write Data Reverse
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//Calcluate CRC checksum, using config's last value as CRC seed
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crc_result = nu_crc_run(u32OpMode, ctx->crc_cfg.last_val, u32CRCAttr, (uint8_t *)in, length);
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//update CRC result to config's last vaule
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ctx->crc_cfg.last_val = crc_result;
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return crc_result ^ 0x00 ^ ctx->crc_cfg.xorout;
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}
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#endif
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