482 lines
14 KiB
ArmAsm
482 lines
14 KiB
ArmAsm
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/*
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* File : start.S
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2016/3/9 16:27:48 louis first version
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*/
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#define CONFIG_STACKSIZE 512
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#define S_FRAME_SIZE 72
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#define S_OLD_R0 68
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#define S_PSR 64
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#define S_PC 60
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#define S_LR 56
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#define S_SP 52
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#define S_IP 48
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#define S_FP 44
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#define S_R10 40
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#define S_R9 36
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#define S_R8 32
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#define S_R7 28
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#define S_R6 24
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#define S_R5 20
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#define S_R4 16
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#define S_R3 12
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#define S_R2 8
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#define S_R1 4
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#define S_R0 0
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.equ USERMODE, 0x10
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.equ FIQMODE, 0x11
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.equ IRQMODE, 0x12
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.equ SVCMODE, 0x13
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.equ ABORTMODE, 0x17
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.equ UNDEFMODE, 0x1b
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.equ MODEMASK, 0x1f
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.equ NOINT, 0xc0
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.text
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.section ".ARM1176START"
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.code 32
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@*******************************************************************************
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@** Common cpu modes
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@*******************************************************************************
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.equ ARM1176_MODE_USR, 0x10 @ CPSR_c xxx10000
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.equ ARM1176_MODE_FIQ, 0x11 @ CPSR_c xxx10001
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.equ ARM1176_MODE_IRQ, 0x12 @ CPSR_c xxx10010
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.equ ARM1176_MODE_SVC, 0x13 @ CPSR_c xxx10011
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.equ ARM1176_MODE_ABT, 0x17 @ CPSR_c xxx10111
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.equ ARM1176_MODE_UND, 0x1B @ CPSR_c xxx11011
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.equ ARM1176_MODE_SYS, 0x1F @ CPSR_c xxx11111
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.equ ARM1176_CPSR_I_BIT, 0x80 @ CPSR_c 100xxxxx
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.equ ARM1176_CPSR_F_BIT, 0x40 @ CPSR_c 010xxxxx
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.equ ARM1176_CPSR_T_BIT, 0x20 @ CPSR_c 001xxxxx
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.globl _start
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.globl ARM1176_Start
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_start:
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ARM1176_Start:
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msr cpsr_c,#(ARM1176_MODE_SYS | ARM1176_CPSR_I_BIT | ARM1176_CPSR_F_BIT) @disable irq/fiq first
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ldr r0, =Reset ;@load translation table base address
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mcr p15,0,r0,c12,c0,0 ;@write translation table base address req
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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Reset:
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ldr pc, =reset
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ldr pc, =vector_undef
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ldr pc, =vector_swi
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ldr pc, =vector_pabt
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ldr pc, =vector_dabt
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ldr pc, =vector_resv
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ldr pc, =vector_irq
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ldr pc, =vector_fiq
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nop
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nop
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.balignl 16,0xdeadbeef
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/*
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*************************************************************************
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*
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* Startup Code (reset vector)
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* relocate armboot to ram
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* setup stack
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* jump to second stage
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*
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*************************************************************************
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*/
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/*
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* rtthread bss start and end which are defined in linker script
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*/
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.extern __stack_start__
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.equ Mode_USR, 0x10
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.equ Mode_FIQ, 0x11
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.equ Mode_IRQ, 0x12
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.equ Mode_SVC, 0x13
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.equ Mode_ABT, 0x17
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.equ Mode_UND, 0x1B
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.equ Mode_SYS, 0x1F
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.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled
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.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled
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.equ UND_Stack_Size, 0x00000200
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.equ SVC_Stack_Size, 0x00000200
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.equ ABT_Stack_Size, 0x00000000
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.equ FIQ_Stack_Size, 0x00000000
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.equ IRQ_Stack_Size, 0x00000200
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.equ USR_Stack_Size, 0x00000200
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#define ISR_Stack_Size (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
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FIQ_Stack_Size + IRQ_Stack_Size)
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.globl stack_top
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stack_top:
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.word __stack_start__
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.extern ARM1176_TcmInitialise
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.extern ARM1176_MmuInitialise
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.extern GH_VIC_set_EdgeClr
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.extern entry
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/*
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*************************************************************************
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*
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* Jump vector table
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*
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*************************************************************************
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*/
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/* ----------------------------------entry------------------------------*/
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reset:
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msr cpsr_c,#(ARM1176_MODE_SYS | ARM1176_CPSR_I_BIT | ARM1176_CPSR_F_BIT) @disable irq/fiq first
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@/* First read in some misc registers */
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mrc p15, 0, r0, c0, c0, 0 @/* Read ID value {A5S=0x41 1 7 b36 5}*/
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mrc p15, 0, r1, c0, c0, 1 @/* Read cache type {0x1d152152}*/
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mrc p15, 0, r2, c0, c0, 2 @/* Read TCM status {0x10001}*/
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#ifdef GK7102C
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@mrc p15, 0, r0, c15,c14,0 @ read CP15 register c15 into r0
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@orr r0, r0,#0x80000000 @ system bit enabled
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@bic r0, r0,#0x00000077 @
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@orr r0, r0,#0x00000055 @ specifies 16KB data cache
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@mcr p15, 0, r0, c15,c14,0 @ wraite CP15 register c15 into r0
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mrc p15, 0, r0, c1, c0, 1 @read CP15 register c1 into r0
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orr r0, r0,#0x00000040 @CZ bit enabled
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mcr p15, 0, r0, c1, c0, 1 @read CP15 register c1 into r0
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#endif
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@/* Turn on instrucion cache and disable MMU */
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mrc p15, 0, r0, c1, c0, 0 @/* Read control register {0x5327d}*/
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@bic r0, r0, #0x1000 @ Turn off bit 12 - I-cache
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orr r0, r0, #0x1000 @ Turn on bit 12 - I-cache
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@bic r0, r0, #0x0004 @ Turn off bit 03 - D-cache
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orr r0, r0, #0x0004 @ Turn on bit 03 - D-cache
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bic r0, r0, #0x2000 @ Turn off bit 13 - HV
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bic r0, r0, #0x0001 @ Turn off bit 1 - MMU
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@orr r0, r0, #0x2 @ Turn on bit 1 - Alignment fault
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bic r0, r0, #0x400000 @ Turn off bit 22 - Unainged support
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@bic r0, r0, #0x2 @ Turn off bit 1 - Alignment fault
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@orr r0, r0, #0x400000 @ Turn on bit 22 - Unainged support
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mcr p15, 0, r0, c1, c0, 0 @/* Write control register */
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mov r0, #0x1
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mcr p15, 0, r0, c3, c0, 0 @/* Write domain access control reg */
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@bl switch_core_freq @/* Change PLL for core if necessary */
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@bl memsetup5 @/* Initialize Memory */
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@/* -------------------------------------------------- */
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@/* Redirect peripheral port 0x60000000 - 0x7fffffff */
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@/* -------------------------------------------------- */
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.if CPU_USE_GK710XS==1
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mov r0, #0x80000000
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orr r0, r0, #0x00000015 @0x14=512M
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.else
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mov r0, #0x60000000
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orr r0, r0, #0x00000014 @0x14=512M
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.endif
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mcr p15, 0, r0, c15, c2, 4
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@ clear the irq or fiq first
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mov r0,#0x0
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mov r1,#0xFFFFFFFF
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bl GH_VIC_set_EdgeClr
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mov r0,#0x1
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mov r1,#0xFFFFFFFF
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bl GH_VIC_set_EdgeClr
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nop
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@ bl ARM1176_TcmInitialise
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msr cpsr_c,#(ARM1176_MODE_SYS | ARM1176_CPSR_I_BIT | ARM1176_CPSR_F_BIT) @disable irq/fiq first
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.if ARM1176_USE_VFP == 1
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bl ARM1176_VfpInitialise
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bl ARM1176_VfpSetFastmode
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.endif
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bl ARM1176_Invalid_Cache
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/* setup stack */
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ldr r0, =stack_top
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ldr r0, [r0]
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@ Enter Undefined Instruction Mode and set its Stack Pointer
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msr cpsr_c, #Mode_UND|I_Bit|F_Bit
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mov sp, r0
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sub r0, r0, #UND_Stack_Size
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@ Enter Abort Mode and set its Stack Pointer
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msr cpsr_c, #Mode_ABT|I_Bit|F_Bit
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mov sp, r0
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sub r0, r0, #ABT_Stack_Size
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@ Enter FIQ Mode and set its Stack Pointer
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msr cpsr_c, #Mode_FIQ|I_Bit|F_Bit
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mov sp, r0
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sub r0, r0, #FIQ_Stack_Size
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@ Enter IRQ Mode and set its Stack Pointer
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msr cpsr_c, #Mode_IRQ|I_Bit|F_Bit
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mov sp, r0
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sub r0, r0, #IRQ_Stack_Size
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@ Enter Supervisor Mode and set its Stack Pointer
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msr cpsr_c, #Mode_SVC|I_Bit|F_Bit
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mov sp, r0
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sub r0, r0, #SVC_Stack_Size
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@ Enter User Mode and set its Stack Pointer
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mov sp, r0
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sub sl, sp, #USR_Stack_Size
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/* clear .bss */
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mov r0,#0 /* get a zero */
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ldr r1,=__bss_start__ /* bss start */
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ldr r2,=__bss_end__ /* bss end */
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bss_loop:
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cmp r1,r2 /* check if data to clear */
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strlo r0,[r1],#4 /* clear 4 bytes */
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blo bss_loop /* loop until done */
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/* call C++ constructors of global objects */
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ldr r0, =__ctors_start__
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ldr r1, =__ctors_end__
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ctor_loop:
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cmp r0, r1
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beq ctor_end
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ldr r2, [r0], #4
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stmfd sp!, {r0-r1}
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mov lr, pc
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bx r2
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ldmfd sp!, {r0-r1}
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b ctor_loop
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ctor_end:
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@ need nocache buffer
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bl ARM1176_MmuInitialise
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/* start RT-Thread Kernel */
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ldr pc, =entry
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.global ARM1176_Invalid_Cache
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.func ARM1176_Invalid_Cache
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ARM1176_Invalid_Cache:
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stmfd sp!,{r0-r12,lr}
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mov r11,lr
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mov r0,#0x0 @Set [31:30]
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mov r1,#0x3
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loop1:
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mov r2,#0x0
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mov r3,#0x80
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loop2:
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mov r4,r0,LSL #30
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mov r5,r2,LSL #5 @Index [S+4:5] S=8 32K
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add r4,r4,r5
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mcr p15, 0, r4, c7, c5, 2
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add r2,r2,#0x1
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cmp r2,r3
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bne loop2
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add r0,r0,#1
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cmp r0,r1
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bne loop1
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mov lr,r11 @ restore link register
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ldmfd sp!,{r0-r12,lr}
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bx lr @ branch back to caller
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.size ARM1176_Invalid_Cache, . - ARM1176_Invalid_Cache
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.endfunc
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.global cpu_reset
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cpu_reset:
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mov pc, lr
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/*
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*************************************************************************
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*
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* Interrupt handling
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*
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*************************************************************************
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*/
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/* exception handlers */
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.align 5
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vector_undef:
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sub sp, sp, #S_FRAME_SIZE
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stmia sp, {r0 - r12} /* Calling r0-r12 */
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add r8, sp, #S_PC
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stmdb r8, {sp, lr}^ /* Calling SP, LR */
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str lr, [r8, #0] /* Save calling PC */
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mrs r6, spsr
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str r6, [r8, #4] /* Save CPSR */
|
||
|
|
str r0, [r8, #8] /* Save OLD_R0 */
|
||
|
|
mov r0, sp
|
||
|
|
|
||
|
|
bl rt_hw_trap_udef
|
||
|
|
|
||
|
|
.align 5
|
||
|
|
vector_swi:
|
||
|
|
bl rt_hw_trap_swi
|
||
|
|
|
||
|
|
.align 5
|
||
|
|
vector_pabt:
|
||
|
|
bl rt_hw_trap_pabt
|
||
|
|
|
||
|
|
.align 5
|
||
|
|
vector_dabt:
|
||
|
|
sub sp, sp, #S_FRAME_SIZE
|
||
|
|
stmia sp, {r0 - r12} /* Calling r0-r12 */
|
||
|
|
add r8, sp, #S_PC
|
||
|
|
stmdb r8, {sp, lr}^ /* Calling SP, LR */
|
||
|
|
str lr, [r8, #0] /* Save calling PC */
|
||
|
|
mrs r6, spsr
|
||
|
|
str r6, [r8, #4] /* Save CPSR */
|
||
|
|
str r0, [r8, #8] /* Save OLD_R0 */
|
||
|
|
mov r0, sp
|
||
|
|
|
||
|
|
bl rt_hw_trap_dabt
|
||
|
|
|
||
|
|
.align 5
|
||
|
|
vector_resv:
|
||
|
|
bl rt_hw_trap_resv
|
||
|
|
|
||
|
|
.align 5
|
||
|
|
.globl rt_interrupt_enter
|
||
|
|
.globl rt_interrupt_leave
|
||
|
|
.globl rt_thread_switch_interrupt_flag
|
||
|
|
.globl rt_interrupt_from_thread
|
||
|
|
.globl rt_interrupt_to_thread
|
||
|
|
vector_irq:
|
||
|
|
stmfd sp!, {r0-r12,lr}
|
||
|
|
bl rt_interrupt_enter
|
||
|
|
bl rt_hw_trap_irq
|
||
|
|
bl rt_interrupt_leave
|
||
|
|
|
||
|
|
/* if rt_thread_switch_interrupt_flag set, jump to _interrupt_thread_switch and don't return */
|
||
|
|
ldr r0, =rt_thread_switch_interrupt_flag
|
||
|
|
ldr r1, [r0]
|
||
|
|
cmp r1, #1
|
||
|
|
beq _interrupt_thread_switch
|
||
|
|
|
||
|
|
ldmfd sp!, {r0-r12,lr}
|
||
|
|
subs pc, lr, #4
|
||
|
|
|
||
|
|
.align 5
|
||
|
|
vector_fiq:
|
||
|
|
stmfd sp!,{r0-r7,lr}
|
||
|
|
bl rt_hw_trap_fiq
|
||
|
|
ldmfd sp!,{r0-r7,lr}
|
||
|
|
subs pc,lr,#4
|
||
|
|
|
||
|
|
_interrupt_thread_switch:
|
||
|
|
mov r1, #0 /* clear rt_thread_switch_interrupt_flag*/
|
||
|
|
str r1, [r0]
|
||
|
|
|
||
|
|
ldmfd sp!, {r0-r12,lr} /* reload saved registers */
|
||
|
|
stmfd sp!, {r0-r3} /* save r0-r3 */
|
||
|
|
mov r1, sp
|
||
|
|
add sp, sp, #16 /* restore sp */
|
||
|
|
sub r2, lr, #4 /* save old task's pc to r2 */
|
||
|
|
|
||
|
|
mrs r3, spsr /* disable interrupt */
|
||
|
|
orr r0, r3, #NOINT
|
||
|
|
msr spsr_c, r0
|
||
|
|
|
||
|
|
ldr r0, =.+8 /* switch to interrupted task's stack*/
|
||
|
|
movs pc, r0
|
||
|
|
|
||
|
|
stmfd sp!, {r2} /* push old task's pc */
|
||
|
|
stmfd sp!, {r4-r12,lr} /* push old task's lr,r12-r4 */
|
||
|
|
mov r4, r1 /* Special optimised code below */
|
||
|
|
mov r5, r3
|
||
|
|
ldmfd r4!, {r0-r3}
|
||
|
|
stmfd sp!, {r0-r3} /* push old task's r3-r0 */
|
||
|
|
stmfd sp!, {r5} /* push old task's psr */
|
||
|
|
mrs r4, spsr
|
||
|
|
stmfd sp!, {r4} /* push old task's spsr */
|
||
|
|
|
||
|
|
ldr r4, =rt_interrupt_from_thread
|
||
|
|
ldr r5, [r4]
|
||
|
|
str sp, [r5] /* store sp in preempted tasks's TCB*/
|
||
|
|
|
||
|
|
ldr r6, =rt_interrupt_to_thread
|
||
|
|
ldr r6, [r6]
|
||
|
|
ldr sp, [r6] /* get new task's stack pointer */
|
||
|
|
|
||
|
|
ldmfd sp!, {r4} /* pop new task's spsr */
|
||
|
|
msr SPSR_cxsf, r4
|
||
|
|
ldmfd sp!, {r4} /* pop new task's psr */
|
||
|
|
msr CPSR_cxsf, r4
|
||
|
|
|
||
|
|
ldmfd sp!, {r0-r12,lr,pc} /* pop new task's r0-r12,lr & pc */
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
@*******************************************************************************
|
||
|
|
@** End of file
|
||
|
|
@*******************************************************************************
|
||
|
|
|