495 lines
19 KiB
C
495 lines
19 KiB
C
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/*
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* The Clear BSD License
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _FSL_CACHE_H_
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#define _FSL_CACHE_H_
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#include "fsl_common.h"
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/*!
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* @addtogroup cache
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @name Driver version */
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/*@{*/
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/*! @brief cache driver version 2.0.1. */
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#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
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/*@}*/
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#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
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#ifndef FSL_SDK_DISBLE_L2CACHE_PRESENT
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#define FSL_SDK_DISBLE_L2CACHE_PRESENT 0
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#endif
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#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
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/*! @brief Number of level 2 cache controller ways. */
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typedef enum _l2cache_way_num
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{
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kL2CACHE_8ways = 0, /*!< 8 ways. */
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#if defined(FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY) && FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY
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kL2CACHE_16ways /*!< 16 ways. */
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#endif /* FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY */
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} l2cache_way_num_t;
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/*! @brief Level 2 cache controller way size. */
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typedef enum _l2cache_way_size
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{
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kL2CACHE_16KBSize = 1, /*!< 16 KB way size. */
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kL2CACHE_32KBSize = 2, /*!< 32 KB way size. */
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kL2CACHE_64KBSize = 3, /*!< 64 KB way size. */
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kL2CACHE_128KBSize = 4, /*!< 128 KB way size. */
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kL2CACHE_256KBSize = 5, /*!< 256 KB way size. */
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kL2CACHE_512KBSize = 6 /*!< 512 KB way size. */
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} l2cache_way_size;
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/*! @brief Level 2 cache controller replacement policy. */
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typedef enum _l2cache_replacement
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{
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kL2CACHE_Pseudorandom = 0U, /*!< Peseudo-random replacement policy using an lfsr. */
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kL2CACHE_Roundrobin /*!< Round-robin replacemnt policy. */
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} l2cache_replacement_t;
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/*! @brief Level 2 cache controller force write allocate options. */
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typedef enum _l2cache_writealloc
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{
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kL2CACHE_UseAwcache = 0, /*!< Use AWCAHE attribute for the write allocate. */
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kL2CACHE_NoWriteallocate, /*!< Force no write allocate. */
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kL2CACHE_forceWriteallocate /*!< Force write allocate when write misses. */
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} l2cache_writealloc_t;
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/*! @brief Level 2 cache controller tag/data ram latency. */
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typedef enum _l2cache_latency
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{
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kL2CACHE_1CycleLate = 0, /*!< 1 cycle of latency. */
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kL2CACHE_2CycleLate, /*!< 2 cycle of latency. */
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kL2CACHE_3CycleLate, /*!< 3 cycle of latency. */
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kL2CACHE_4CycleLate, /*!< 4 cycle of latency. */
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kL2CACHE_5CycleLate, /*!< 5 cycle of latency. */
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kL2CACHE_6CycleLate, /*!< 6 cycle of latency. */
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kL2CACHE_7CycleLate, /*!< 7 cycle of latency. */
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kL2CACHE_8CycleLate /*!< 8 cycle of latency. */
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} l2cache_latency_t;
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/*! @brief Level 2 cache controller tag/data ram latency configure structure. */
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typedef struct _l2cache_latency_config
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{
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l2cache_latency_t tagWriteLate; /*!< Tag write latency. */
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l2cache_latency_t tagReadLate; /*!< Tag Read latency. */
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l2cache_latency_t tagSetupLate; /*!< Tag setup latency. */
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l2cache_latency_t dataWriteLate; /*!< Data write latency. */
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l2cache_latency_t dataReadLate; /*!< Data Read latency. */
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l2cache_latency_t dataSetupLate; /*!< Data setup latency. */
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} L2cache_latency_config_t;
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/*! @brief Level 2 cache controller configure structure. */
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typedef struct _l2cache_config
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{
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/* ------------------------ l2 cachec basic settings ---------------------------- */
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l2cache_way_num_t wayNum; /*!< The number of ways. */
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l2cache_way_size waySize; /*!< The way size = Cache Ram size / wayNum. */
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l2cache_replacement_t repacePolicy;/*!< Replacemnet policy. */
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/* ------------------------ tag/data ram latency settings ----------------------- */
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L2cache_latency_config_t *lateConfig; /*!< Tag/data latency configure. Set NUll if not required. */
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/* ------------------------ Prefetch enable settings ---------------------------- */
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bool istrPrefetchEnable; /*!< Instruction prefetch enable. */
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bool dataPrefetchEnable; /*!< Data prefetch enable. */
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/* ------------------------ Non-secure access settings -------------------------- */
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bool nsLockdownEnable; /*!< None-secure lockdown enable. */
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/* ------------------------ other settings -------------------------------------- */
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l2cache_writealloc_t writeAlloc;/*!< Write allcoate force option. */
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} l2cache_config_t;
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#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
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/*******************************************************************************
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* API
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/*!
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* @name Control for cortex-m7 L1 cache
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*@{
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*/
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/*!
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* @brief Enables cortex-m7 L1 instruction cache.
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*
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*/
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static inline void L1CACHE_EnableICache(void)
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{
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SCB_EnableICache();
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}
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/*!
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* @brief Disables cortex-m7 L1 instruction cache.
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*
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*/
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static inline void L1CACHE_DisableICache(void)
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{
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SCB_DisableICache();
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}
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/*!
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* @brief Invalidate cortex-m7 L1 instruction cache.
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*
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*/
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static inline void L1CACHE_InvalidateICache(void)
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{
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SCB_InvalidateICache();
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}
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/*!
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* @brief Invalidate cortex-m7 L1 instruction cache by range.
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*
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* @param address The start address of the memory to be invalidated.
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* @param size_byte The memory size.
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* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.
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* The startAddr here will be forced to align to L1 I-cache line size if
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* startAddr is not aligned. For the size_byte, application should make sure the
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* alignment or make sure the right operation order if the size_byte is not aligned.
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*/
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void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte);
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/*!
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* @brief Enables cortex-m7 L1 data cache.
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*
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*/
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static inline void L1CACHE_EnableDCache(void)
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{
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SCB_EnableDCache();
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}
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/*!
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* @brief Disables cortex-m7 L1 data cache.
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*
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*/
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static inline void L1CACHE_DisableDCache(void)
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{
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SCB_DisableDCache();
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}
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/*!
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* @brief Invalidates cortex-m7 L1 data cache.
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*
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*/
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static inline void L1CACHE_InvalidateDCache(void)
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{
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SCB_InvalidateDCache();
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}
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/*!
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* @brief Cleans cortex-m7 L1 data cache.
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*
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*/
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static inline void L1CACHE_CleanDCache(void)
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{
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SCB_CleanDCache();
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}
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/*!
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* @brief Cleans and Invalidates cortex-m7 L1 data cache.
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*
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*/
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static inline void L1CACHE_CleanInvalidateDCache(void)
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{
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SCB_CleanInvalidateDCache();
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}
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/*!
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* @brief Invalidates cortex-m7 L1 data cache by range.
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*
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* @param address The start address of the memory to be invalidated.
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* @param size_byte The memory size.
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* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
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* The startAddr here will be forced to align to L1 D-cache line size if
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* startAddr is not aligned. For the size_byte, application should make sure the
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* alignment or make sure the right operation order if the size_byte is not aligned.
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*/
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static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
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{
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uint32_t startAddr = address & (uint32_t)~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1);
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uint32_t size = size_byte + address - startAddr;
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SCB_InvalidateDCache_by_Addr((uint32_t *)startAddr, size);
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}
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/*!
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* @brief Cleans cortex-m7 L1 data cache by range.
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*
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* @param address The start address of the memory to be cleaned.
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* @param size_byte The memory size.
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* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
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* The startAddr here will be forced to align to L1 D-cache line size if
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* startAddr is not aligned. For the size_byte, application should make sure the
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* alignment or make sure the right operation order if the size_byte is not aligned.
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*/
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static inline void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte)
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{
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uint32_t startAddr = address & (uint32_t)~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1);
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uint32_t size = size_byte + address - startAddr;
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SCB_CleanDCache_by_Addr((uint32_t *)startAddr, size);
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}
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/*!
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* @brief Cleans and Invalidates cortex-m7 L1 data cache by range.
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*
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* @param address The start address of the memory to be clean and invalidated.
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* @param size_byte The memory size.
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* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
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* The startAddr here will be forced to align to L1 D-cache line size if
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* startAddr is not aligned. For the size_byte, application should make sure the
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* alignment or make sure the right operation order if the size_byte is not aligned.
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*/
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static inline void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
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{
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uint32_t startAddr = address & (uint32_t)~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1);
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uint32_t size = size_byte + address - startAddr;
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SCB_CleanInvalidateDCache_by_Addr((uint32_t *)startAddr, size);
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}
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/*@}*/
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#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
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/*!
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* @name Control for L2 pl310 cache
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*@{
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*/
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/*!
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* @brief Initializes the level 2 cache controller module.
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*
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* @param config Pointer to configuration structure. See "l2cache_config_t".
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*/
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void L2CACHE_Init(l2cache_config_t *config);
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/*!
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* @brief Gets an available default settings for the cache controller.
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*
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* This function initializes the cache controller configuration structure with default settings.
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* The default values are:
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* @code
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* config->waysNum = kL2CACHE_8ways;
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* config->waySize = kL2CACHE_32KbSize;
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* config->repacePolicy = kL2CACHE_Roundrobin;
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* config->lateConfig = NULL;
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* config->istrPrefetchEnable = false;
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* config->dataPrefetchEnable = false;
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* config->nsLockdownEnable = false;
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* config->writeAlloc = kL2CACHE_UseAwcache;
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* @endcode
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* @param config Pointer to the configuration structure.
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*/
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void L2CACHE_GetDefaultConfig(l2cache_config_t *config);
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/*!
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* @brief Enables the level 2 cache controller.
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* This function enables the cache controller. Must be written using a secure access.
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* If write with a Non-secure access will cause a DECERR response.
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*
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*/
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void L2CACHE_Enable(void);
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/*!
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* @brief Disables the level 2 cache controller.
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* This function disables the cache controller. Must be written using a secure access.
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* If write with a Non-secure access will cause a DECERR response.
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*
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*/
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void L2CACHE_Disable(void);
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/*!
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* @brief Invalidates the Level 2 cache.
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* This function invalidates all entries in cache.
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*
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*/
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void L2CACHE_Invalidate(void);
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/*!
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* @brief Invalidates the Level 2 cache lines in the range of two physical addresses.
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* This function invalidates all cache lines between two physical addresses.
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*
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* @param address The start address of the memory to be invalidated.
|
||
|
|
* @param size_byte The memory size.
|
||
|
|
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
|
||
|
|
* The startAddr here will be forced to align to L2 line size if startAddr
|
||
|
|
* is not aligned. For the size_byte, application should make sure the
|
||
|
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||
|
|
*/
|
||
|
|
void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte);
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Cleans the level 2 cache controller.
|
||
|
|
* This function cleans all entries in the level 2 cache controller.
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
void L2CACHE_Clean(void);
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Cleans the Level 2 cache lines in the range of two physical addresses.
|
||
|
|
* This function cleans all cache lines between two physical addresses.
|
||
|
|
*
|
||
|
|
* @param address The start address of the memory to be cleaned.
|
||
|
|
* @param size_byte The memory size.
|
||
|
|
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
|
||
|
|
* The startAddr here will be forced to align to L2 line size if startAddr
|
||
|
|
* is not aligned. For the size_byte, application should make sure the
|
||
|
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||
|
|
*/
|
||
|
|
void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte);
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Cleans and invalidates the level 2 cache controller.
|
||
|
|
* This function cleans and invalidates all entries in the level 2 cache controller.
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
void L2CACHE_CleanInvalidate(void);
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Cleans and invalidates the Level 2 cache lines in the range of two physical addresses.
|
||
|
|
* This function cleans and invalidates all cache lines between two physical addresses.
|
||
|
|
*
|
||
|
|
* @param address The start address of the memory to be cleaned and invalidated.
|
||
|
|
* @param size_byte The memory size.
|
||
|
|
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
|
||
|
|
* The startAddr here will be forced to align to L2 line size if startAddr
|
||
|
|
* is not aligned. For the size_byte, application should make sure the
|
||
|
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||
|
|
*/
|
||
|
|
void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte);
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Enables or disables to lock down the data and instruction by way.
|
||
|
|
* This function locks down the cached instruction/data by way and prevent the adresses from
|
||
|
|
* being allocated and prevent dara from being evicted out of the level 2 cache.
|
||
|
|
* But the normal cache maintenance operations that invalidate, clean or clean
|
||
|
|
* and validate cache contents affect the locked-down cache lines as normal.
|
||
|
|
*
|
||
|
|
* @param masterId The master id, range from 0 ~ 7.
|
||
|
|
* @param mask The ways to be enabled or disabled to lockdown.
|
||
|
|
* each bit in value is related to each way of the cache. for example:
|
||
|
|
* value: bit 0 ------ way 0.
|
||
|
|
* value: bit 1 ------ way 1.
|
||
|
|
* --------------------------
|
||
|
|
* value: bit 15 ------ way 15.
|
||
|
|
* Note: please make sure the value setting is align with your supported ways.
|
||
|
|
* @param enable True enable the lockdown, false to disable the lockdown.
|
||
|
|
*/
|
||
|
|
void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable);
|
||
|
|
|
||
|
|
/*@}*/
|
||
|
|
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @name Unified Cache Control for all caches (cortex-m7 L1 cache + l2 pl310)
|
||
|
|
* Mainly used for many drivers for easy cache operation.
|
||
|
|
*@{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Invalidates all instruction caches by range.
|
||
|
|
*
|
||
|
|
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
|
||
|
|
*
|
||
|
|
* @param address The physical address.
|
||
|
|
* @param size_byte size of the memory to be invalidated.
|
||
|
|
* @note address and size should be aligned to cache line size
|
||
|
|
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
|
||
|
|
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
|
||
|
|
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
|
||
|
|
*/
|
||
|
|
void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte);
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Invalidates all data caches by range.
|
||
|
|
*
|
||
|
|
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
|
||
|
|
*
|
||
|
|
* @param address The physical address.
|
||
|
|
* @param size_byte size of the memory to be invalidated.
|
||
|
|
* @note address and size should be aligned to cache line size
|
||
|
|
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
|
||
|
|
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
|
||
|
|
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
|
||
|
|
*/
|
||
|
|
void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte);
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Cleans all data caches by range.
|
||
|
|
*
|
||
|
|
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
|
||
|
|
*
|
||
|
|
* @param address The physical address.
|
||
|
|
* @param size_byte size of the memory to be cleaned.
|
||
|
|
* @note address and size should be aligned to cache line size
|
||
|
|
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
|
||
|
|
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
|
||
|
|
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
|
||
|
|
*/
|
||
|
|
void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte);
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Cleans and Invalidates all data caches by range.
|
||
|
|
*
|
||
|
|
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
|
||
|
|
*
|
||
|
|
* @param address The physical address.
|
||
|
|
* @param size_byte size of the memory to be cleaned and invalidated.
|
||
|
|
* @note address and size should be aligned to cache line size
|
||
|
|
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
|
||
|
|
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
|
||
|
|
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
|
||
|
|
*/
|
||
|
|
void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte);
|
||
|
|
|
||
|
|
/*@}*/
|
||
|
|
|
||
|
|
|
||
|
|
#if defined(__cplusplus)
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/*! @}*/
|
||
|
|
|
||
|
|
#endif /* _FSL_CACHE_H_*/
|