2011-04-05 20:49:01 +08:00
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/*
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* File : at91_rstc.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Develop Team
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*
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2013-07-21 20:01:24 +08:00
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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2011-04-05 20:49:01 +08:00
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*
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* Change Logs:
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* Date Author Notes
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* 2011-01-13 weety first version
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*/
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#ifndef AT91_RSTC_H
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#define AT91_RSTC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */
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#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
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#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */
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#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */
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#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */
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#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */
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#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */
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#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */
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#define AT91_RSTC_RSTTYP_GENERAL (0 << 8)
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#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8)
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#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8)
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#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8)
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#define AT91_RSTC_RSTTYP_USER (4 << 8)
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#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */
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#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */
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#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */
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#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */
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#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */
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#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */
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#ifdef __cplusplus
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}
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#endif
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#endif
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