298 lines
12 KiB
C
298 lines
12 KiB
C
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/*
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* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
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*
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* Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
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* the the People's Republic of China and other countries.
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* All Allwinner Technology Co.,Ltd. trademarks are used with permission.
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*
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* DISCLAIMER
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* THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
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* IF YOU NEED TO INTEGRATE THIRD PARTY¡¯S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
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* IN ALLWINNERS¡¯SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
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* ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
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* ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
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* COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
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* YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY¡¯S TECHNOLOGY.
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*
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*
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* THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
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* PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
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* THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
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* OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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* IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __SUNXI_HAL_DMA_H__
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#define __SUNXI_HAL_DMA_H__
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#include <stdint.h>
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#include <stdbool.h>
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#include <stdio.h>
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/*
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* include the platform dma header file.
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*/
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#include <dma/platform-dma.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* #define DMA_DEBUG */
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#define HEXADECIMAL (0x10)
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#define REG_INTERVAL (0x04)
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#define REG_CL (0x0c)
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//TODO:move reg list to sunxiwxx.h
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#define HIGH_CHAN 8
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#define DMA_IRQ_EN(x) (SUNXI_DMAC_PBASE + (0x00 + ((x) << 2))) /* Interrupt enable register */
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#define DMA_IRQ_STAT(x) (SUNXI_DMAC_PBASE + (0x10 + ((x) << 2))) /* Interrupt status register */
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#define DMA_SECURE (SUNXI_DMAC_PBASE + 0x20) /* DMA security register */
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#define DMA_GATE (SUNXI_DMAC_PBASE + 0x28) /* DMA gating register */
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#define DMA_MCLK_GATE 0x04
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#define DMA_COMMON_GATE 0x02
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#define DMA_CHAN_GATE 0x01
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#define DMA_STAT (SUNXI_DMAC_PBASE + 0x30) /* DMA Status Register RO */
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#define DMA_ENABLE(x) (SUNXI_DMAC_PBASE + (0x100 + ((x + START_CHAN_OFFSET) << 6))) /* Channels enable register */
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#define DMA_PAUSE(x) (SUNXI_DMAC_PBASE + (0x104 + ((x + START_CHAN_OFFSET) << 6))) /* DMA Channels pause register */
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#define DMA_LLI_ADDR(x) (SUNXI_DMAC_PBASE + (0x108 + ((x + START_CHAN_OFFSET) << 6))) /* Descriptor address register */
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#define DMA_CFG(x) (SUNXI_DMAC_PBASE + (0x10C + ((x + START_CHAN_OFFSET) << 6))) /* Configuration register RO */
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#define DMA_CUR_SRC(x) (SUNXI_DMAC_PBASE + (0x110 + ((x + START_CHAN_OFFSET) << 6))) /* Current source address RO */
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#define DMA_CUR_DST(x) (SUNXI_DMAC_PBASE + (0x114 + ((x + START_CHAN_OFFSET) << 6))) /* Current destination address RO */
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#define DMA_CNT(x) (SUNXI_DMAC_PBASE + (0x118 + ((x + START_CHAN_OFFSET) << 6))) /* Byte counter left register RO */
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#define DMA_PARA(x) (SUNXI_DMAC_PBASE + (0x11C + ((x + START_CHAN_OFFSET) << 6))) /* Parameter register RO */
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#define LINK_END 0xFFFFF800 /* lastest link must be 0xfffff800 */
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/* DMA mode register */
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#define DMA_OP_MODE(x) (SUNXI_DMAC_PBASE + (0x128 + ((x + START_CHAN_OFFSET) << 6))) /* DMA mode register */
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#define SRC_HS_MASK (0x1 << 2) /* bit 2: Source handshake mode */
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#define DST_HS_MASK (0x1 << 3) /* bit 3: Destination handshake mode */
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#define SET_OP_MODE(x, val) ({ \
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writel(val,DMA_OP_MODE(x)); \
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})
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#define SHIFT_IRQ_MASK(val, ch) ({ \
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(ch + START_CHAN_OFFSET) >= HIGH_CHAN \
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? (val) << ((ch + START_CHAN_OFFSET - HIGH_CHAN) << 2) \
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: (val) << ((ch + START_CHAN_OFFSET) << 2); \
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})
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#define SHIFT_PENDING_MASK(val, ch) ({ \
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(ch + START_CHAN_OFFSET) >= HIGH_CHAN \
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? (val) << ((ch + START_CHAN_OFFSET - HIGH_CHAN) << 2) \
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: (val) << ((ch + START_CHAN_OFFSET) << 2); \
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})
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#define IRQ_HALF 0x01 /* Half package transfer interrupt pending */
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#define IRQ_PKG 0x02 /* One package complete interrupt pending */
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#define IRQ_QUEUE 0x04 /* All list complete transfer interrupt pending */
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/* DMA channel configuration register */
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/* The detail information of DMA configuration */
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#define SRC_WIDTH(x) ((x) << 9)
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#define SRC_BURST(x) ((x) << 6)
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#define SRC_IO_MODE (0x01 << 8)
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#define SRC_LINEAR_MODE (0x00 << 8)
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#define SRC_DRQ(x) ((x) << 0)
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#define DST_WIDTH(x) ((x) << 25)
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#define DST_BURST(x) ((x) << 22)
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#define DST_IO_MODE (0x01 << 24)
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#define DST_LINEAR_MODE (0x00 << 24)
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#define DST_DRQ(x) ((x) << 16)
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#define CHAN_START 1
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#define CHAN_STOP 0
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#define CHAN_PAUSE 1
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#define CHAN_RESUME 0
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#define NORMAL_WAIT (8 << 0)
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#define GET_SRC_DRQ(x) ((x) & 0x000000ff)
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#define GET_DST_DRQ(x) ((x) & 0x00ff0000)
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struct sunxi_dma_lli {
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uint32_t cfg;
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uint32_t src;
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uint32_t dst;
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uint32_t len;
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uint32_t para;
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uint32_t p_lln;
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struct sunxi_dma_lli *vlln;
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};
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#define sunxi_slave_id(d, s) (((d)<<16) | (s))
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typedef void (*dma_callback)(void *param);
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/**
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* enum dma_slave_buswidth - defines bus width of the DMA slave
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* device, source or target buses
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*/
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enum dma_slave_buswidth {
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DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
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DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
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DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
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DMA_SLAVE_BUSWIDTH_3_BYTES = 3,
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DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
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DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
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DMA_SLAVE_BUSWIDTH_16_BYTES = 16,
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DMA_SLAVE_BUSWIDTH_32_BYTES = 32,
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DMA_SLAVE_BUSWIDTH_64_BYTES = 64,
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};
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enum dma_slave_burst {
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DMA_SLAVE_BURST_1 = 1,
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DMA_SLAVE_BURST_4 = 4,
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DMA_SLAVE_BURST_8 = 8,
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DMA_SLAVE_BURST_16 = 16,
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};
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/**
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* enum dma_transfer_direction - dma transfer mode and direction indicator
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* @DMA_MEM_TO_MEM: Async/Memcpy mode
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* @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
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* @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
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* @DMA_DEV_TO_DEV: Slave mode & From Device to Device
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*/
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enum dma_transfer_direction {
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DMA_MEM_TO_MEM = 0,
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DMA_MEM_TO_DEV = 1,
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DMA_DEV_TO_MEM = 2,
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DMA_DEV_TO_DEV = 3,
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DMA_TRANS_NONE,
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};
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/**
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* enum dma_status - DMA transaction status
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* @DMA_COMPLETE: transaction completed
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* @DMA_IN_PROGRESS: transaction not yet processed
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* @DMA_PAUSED: transaction is paused
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* @DMA_ERROR: transaction failed
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*/
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enum dma_status {
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DMA_INVALID_PARAMETER = -2,
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DMA_ERROR = -1,
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DMA_COMPLETE,
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DMA_IN_PROGRESS,
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DMA_PAUSED,
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};
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/**
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* struct dma_slave_config - dma slave channel runtime config
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* @direction: whether the data shall go in or out on this slave
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* channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are
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* legal values. DEPRECATED, drivers should use the direction argument
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* to the device_prep_slave_sg and device_prep_dma_cyclic functions or
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* the dir field in the dma_interleaved_template structure.
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* @src_addr: this is the physical address where DMA slave data
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* should be read (RX), if the source is memory this argument is
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* ignored.
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* @dst_addr: this is the physical address where DMA slave data
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* should be written (TX), if the source is memory this argument
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* is ignored.
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* @src_addr_width: this is the width in bytes of the source (RX)
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* register where DMA data shall be read. If the source
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* is memory this may be ignored depending on architecture.
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* Legal values: 1, 2, 4, 8.
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* @dst_addr_width: same as src_addr_width but for destination
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* target (TX) mutatis mutandis.
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* @src_maxburst: the maximum number of words (note: words, as in
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* units of the src_addr_width member, not bytes) that can be sent
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* in one burst to the device. Typically something like half the
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* FIFO depth on I/O peripherals so you don't overflow it. This
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* may or may not be applicable on memory sources.
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* @dst_maxburst: same as src_maxburst but for destination target
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* mutatis mutandis.
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* @slave_id: Slave requester id. Only valid for slave channels. The dma
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* slave peripheral will have unique id as dma requester which need to be
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* pass as slave config.
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*
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* This struct is passed in as configuration data to a DMA engine
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* in order to set up a certain channel for DMA transport at runtime.
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* The DMA device/engine has to provide support for an additional
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* callback in the dma_device structure, device_config and this struct
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* will then be passed in as an argument to the function.
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*
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* The rationale for adding configuration information to this struct is as
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* follows: if it is likely that more than one DMA slave controllers in
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* the world will support the configuration option, then make it generic.
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* If not: if it is fixed so that it be sent in static from the platform
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* data, then prefer to do that.
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*/
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struct dma_slave_config {
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enum dma_transfer_direction direction;
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unsigned long src_addr;
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unsigned long dst_addr;
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enum dma_slave_buswidth src_addr_width;
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enum dma_slave_buswidth dst_addr_width;
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uint32_t src_maxburst;
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uint32_t dst_maxburst;
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uint32_t slave_id;
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};
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struct sunxi_dma_chan {
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uint8_t used:1;
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uint8_t chan_count:4;
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bool cyclic:1;
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struct dma_slave_config cfg;
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uint32_t periods_pos;
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uint32_t buf_len;
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struct sunxi_dma_lli *desc;
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uint32_t irq_type;
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dma_callback callback;
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void *callback_param;
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/* volatile kspinlock_t lock; */
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volatile int lock;
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};
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/** This enum defines the DMA CHANNEL status. */
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typedef enum {
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HAL_DMA_CHAN_STATUS_BUSY = 0, /* DMA channel status busy */
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HAL_DMA_CHAN_STATUS_FREE = 1 /* DMA channel status free */
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} hal_dma_chan_status_t;
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/** This enum defines the return type of GPIO API. */
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typedef enum {
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HAL_DMA_STATUS_INVALID_PARAMETER = -22, /* Invalid input parameter. */
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HAL_DMA_STATUS_NO_MEM = -12, /* No memory. */
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HAL_DMA_STATUS_ERR_PERM = -1, /* Operation not permitted. */
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HAL_DMA_STATUS_OK = 0 /* The DMA status ok. */
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} hal_dma_status_t;
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hal_dma_chan_status_t hal_dma_chan_request(struct sunxi_dma_chan **dma_chan);
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hal_dma_status_t hal_dma_prep_memcpy(struct sunxi_dma_chan *chan,
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uint32_t dest, uint32_t src, uint32_t len);
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hal_dma_status_t hal_dma_prep_device(struct sunxi_dma_chan *chan,
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uint32_t dest, uint32_t src,
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uint32_t len, enum dma_transfer_direction dir);
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hal_dma_status_t hal_dma_prep_cyclic(struct sunxi_dma_chan *chan,
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uint32_t buf_addr, uint32_t buf_len,
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uint32_t period_len, enum dma_transfer_direction dir);
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hal_dma_status_t hal_dma_callback_install(struct sunxi_dma_chan *chan,
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dma_callback callback,
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void *callback_param);
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hal_dma_status_t hal_dma_slave_config(struct sunxi_dma_chan *chan, struct dma_slave_config *config);
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enum dma_status hal_dma_tx_status(struct sunxi_dma_chan *chan, uint32_t *left_size);
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hal_dma_status_t hal_dma_start(struct sunxi_dma_chan *chan);
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hal_dma_status_t hal_dma_stop(struct sunxi_dma_chan *chan);
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hal_dma_status_t hal_dma_chan_free(struct sunxi_dma_chan *chan);
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hal_dma_status_t hal_dma_chan_desc_free(struct sunxi_dma_chan *chan);
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void hal_dma_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif
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