2020-04-16 16:10:57 +08:00
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/*
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2023-07-15 15:21:23 +08:00
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* Copyright (c) 2006-2023, RT-Thread Development Team
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2020-04-16 16:10:57 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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2022-12-20 17:49:37 +08:00
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* 2021-05-12 RT-Thread init
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2023-07-15 15:21:23 +08:00
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* 2023-07-13 GuEe-GUI append fpu: Q16 ~ Q31
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2020-04-16 16:10:57 +08:00
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*/
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2022-12-20 17:49:37 +08:00
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#include <board.h>
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2020-04-16 16:10:57 +08:00
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#include <rtthread.h>
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2023-05-14 23:48:16 +08:00
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#include <cpuport.h>
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2022-12-20 17:49:37 +08:00
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2020-04-16 16:10:57 +08:00
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#include <armv8.h>
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2022-12-20 17:49:37 +08:00
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#define INITIAL_SPSR_EL1 (PSTATE_EL1 | SP_ELx)
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2020-04-16 16:10:57 +08:00
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/**
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* This function will initialize thread stack
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*
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* @param tentry the entry of thread
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2021-03-27 17:51:56 +08:00
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* @param parameter the parameter of entry
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2020-04-16 16:10:57 +08:00
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* @param stack_addr the beginning stack address
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* @param texit the function will be called when thread exit
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*
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* @return stack address
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*/
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2022-12-20 17:49:37 +08:00
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rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
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rt_uint8_t *stack_addr, void *texit)
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2020-04-16 16:10:57 +08:00
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{
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2022-12-20 17:49:37 +08:00
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rt_ubase_t *stk;
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2024-04-11 00:02:49 +08:00
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/* The AAPCS64 requires 128-bit (16 byte) stack alignment */
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stk = (rt_ubase_t*)RT_ALIGN_DOWN((rt_ubase_t)stack_addr, 16);
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2022-12-20 17:49:37 +08:00
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2023-07-15 15:21:23 +08:00
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for (int i = 0; i < 32; ++i)
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{
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stk -= sizeof(rt_uint128_t) / sizeof(rt_ubase_t);
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*(rt_uint128_t *)stk = (rt_uint128_t) { 0 };
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}
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2020-04-16 16:10:57 +08:00
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2023-05-14 23:48:16 +08:00
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*(--stk) = (rt_ubase_t)0; /* X1 */
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*(--stk) = (rt_ubase_t)parameter; /* X0 */
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*(--stk) = (rt_ubase_t)3; /* X3 */
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*(--stk) = (rt_ubase_t)2; /* X2 */
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*(--stk) = (rt_ubase_t)5; /* X5 */
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*(--stk) = (rt_ubase_t)4; /* X4 */
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*(--stk) = (rt_ubase_t)7; /* X7 */
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*(--stk) = (rt_ubase_t)6; /* X6 */
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*(--stk) = (rt_ubase_t)9; /* X9 */
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*(--stk) = (rt_ubase_t)8; /* X8 */
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*(--stk) = (rt_ubase_t)11; /* X11 */
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*(--stk) = (rt_ubase_t)10; /* X10 */
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*(--stk) = (rt_ubase_t)13; /* X13 */
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*(--stk) = (rt_ubase_t)12; /* X12 */
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*(--stk) = (rt_ubase_t)15; /* X15 */
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*(--stk) = (rt_ubase_t)14; /* X14 */
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*(--stk) = (rt_ubase_t)17; /* X17 */
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*(--stk) = (rt_ubase_t)16; /* X16 */
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*(--stk) = (rt_ubase_t)tentry; /* X19, 1st param */
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*(--stk) = (rt_ubase_t)18; /* X18 */
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*(--stk) = (rt_ubase_t)21; /* X21 */
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*(--stk) = (rt_ubase_t)texit; /* X20, 2nd param */
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*(--stk) = (rt_ubase_t)23; /* X23 */
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*(--stk) = (rt_ubase_t)22; /* X22 */
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*(--stk) = (rt_ubase_t)25; /* X25 */
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*(--stk) = (rt_ubase_t)24; /* X24 */
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*(--stk) = (rt_ubase_t)27; /* X27 */
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*(--stk) = (rt_ubase_t)26; /* X26 */
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*(--stk) = (rt_ubase_t)0; /* X29 - addr 0 as AAPCS64 specified */
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*(--stk) = (rt_ubase_t)28; /* X28 */
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*(--stk) = (rt_ubase_t)0; /* FPSR */
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*(--stk) = (rt_ubase_t)0; /* FPCR */
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*(--stk) = (rt_ubase_t)0; /* X30 - procedure call link register. */
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*(--stk) = (rt_ubase_t)0; /* sp_el0 */
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2022-01-07 13:49:06 +08:00
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2022-12-20 17:49:37 +08:00
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*(--stk) = INITIAL_SPSR_EL1;
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2020-04-16 16:10:57 +08:00
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2023-05-14 23:48:16 +08:00
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*(--stk) = (rt_ubase_t)_thread_start; /* Exception return address. */
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2020-04-16 16:10:57 +08:00
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2021-03-27 17:51:56 +08:00
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/* return task's current stack address */
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return (rt_uint8_t *)stk;
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2020-04-16 16:10:57 +08:00
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}
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