294 lines
9.3 KiB
C
294 lines
9.3 KiB
C
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/*
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* Copyright 2020 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _FSL_NIC301_H_
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#define _FSL_NIC301_H_
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#include "fsl_common.h"
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/*!
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* @addtogroup nic301
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.nic301"
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#endif
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/*! @name Driver version */
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/*@{*/
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/*! @brief NIC301 driver version 2.0.0. */
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#define FSL_NIC301_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 0U))
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/*@}*/
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#define GPV0_BASE (0x41000000UL)
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#define GPV1_BASE (0x41100000UL)
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#define GPV4_BASE (0x41400000UL)
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#define NIC_FN_MOD_AHB_OFFSET (0x028UL)
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#define NIC_WR_TIDEMARK_OFFSET (0x040UL)
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#define NIC_READ_QOS_OFFSET (0x100UL)
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#define NIC_WRITE_QOS_OFFSET (0x104UL)
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#define NIC_FN_MOD_OFFSET (0x108UL)
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#define NIC_GC355_BASE (GPV0_BASE + 0x42000)
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#define NIC_PXP_BASE (GPV0_BASE + 0x43000)
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#define NIC_LCDIF_BASE (GPV0_BASE + 0x44000)
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#define NIC_LCDIFV2_BASE (GPV0_BASE + 0x45000)
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#define NIC_CSI_BASE (GPV0_BASE + 0x46000)
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#define NIC_CAAM_BASE (GPV1_BASE + 0x42000)
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#define NIC_ENET1G_RX_BASE (GPV1_BASE + 0x43000)
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#define NIC_ENET1G_TX_BASE (GPV1_BASE + 0x44000)
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#define NIC_ENET_BASE (GPV1_BASE + 0x45000)
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#define NIC_USBO2_BASE (GPV1_BASE + 0x46000)
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#define NIC_USDHC1_BASE (GPV1_BASE + 0x47000)
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#define NIC_USDHC2_BASE (GPV1_BASE + 0x48000)
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#define NIC_ENET_QOS_BASE (GPV1_BASE + 0x4A000)
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#define NIC_CM7_BASE (GPV4_BASE + 0x42000)
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#define NIC_LPSRMIX_M_BASE (GPV4_BASE + 0x46000)
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#define NIC_DMA_BASE (GPV4_BASE + 0x47000)
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#define NIC_IEE_BASE (GPV4_BASE + 0x48000)
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#define NIC_QOS_MASK (0xF)
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#define NIC_WR_TIDEMARK_MASK (0xF)
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#define NIC_FN_MOD_AHB_MASK (0x7)
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#define NIC_FN_MOD_MASK (0x1)
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typedef enum _nic_reg
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{
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/* read_qos */
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kNIC_REG_READ_QOS_GC355 = NIC_GC355_BASE + NIC_READ_QOS_OFFSET,
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kNIC_REG_READ_QOS_PXP = NIC_PXP_BASE + NIC_READ_QOS_OFFSET,
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kNIC_REG_READ_QOS_LCDIF = NIC_LCDIF_BASE + NIC_READ_QOS_OFFSET,
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kNIC_REG_READ_QOS_LCDIFV2 = NIC_LCDIFV2_BASE + NIC_READ_QOS_OFFSET,
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kNIC_REG_READ_QOS_CSI = NIC_CSI_BASE + NIC_READ_QOS_OFFSET,
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kNIC_REG_READ_QOS_CAAM = NIC_CAAM_BASE + NIC_READ_QOS_OFFSET,
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kNIC_REG_READ_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_READ_QOS_OFFSET,
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kNIC_REG_READ_QOS_ENET1G_TX = NIC_ENET1G_TX_BASE + NIC_READ_QOS_OFFSET,
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kNIC_REG_READ_QOS_ENET = NIC_ENET_BASE + NIC_READ_QOS_OFFSET,
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kNIC_REG_READ_QOS_USBO2 = NIC_USBO2_BASE + NIC_READ_QOS_OFFSET,
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kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
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kNIC_REG_READ_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_READ_QOS_OFFSET,
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kNIC_REG_READ_QOS_ENET_QOS = NIC_ENET_QOS_BASE + NIC_READ_QOS_OFFSET,
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kNIC_REG_READ_QOS_CM7 = NIC_CM7_BASE + NIC_READ_QOS_OFFSET,
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kNIC_REG_READ_QOS_DMA = NIC_DMA_BASE + NIC_READ_QOS_OFFSET,
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kNIC_REG_READ_QOS_IEE = NIC_IEE_BASE + NIC_READ_QOS_OFFSET,
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/* write_qos */
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kNIC_REG_WRITE_QOS_GC355 = NIC_GC355_BASE + NIC_WRITE_QOS_OFFSET,
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kNIC_REG_WRITE_QOS_PXP = NIC_PXP_BASE + NIC_WRITE_QOS_OFFSET,
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kNIC_REG_WRITE_QOS_LCDIF = NIC_LCDIF_BASE + NIC_WRITE_QOS_OFFSET,
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kNIC_REG_WRITE_QOS_LCDIFV2 = NIC_LCDIFV2_BASE + NIC_WRITE_QOS_OFFSET,
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kNIC_REG_WRITE_QOS_CSI = NIC_CSI_BASE + NIC_WRITE_QOS_OFFSET,
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kNIC_REG_WRITE_QOS_CAAM = NIC_CAAM_BASE + NIC_WRITE_QOS_OFFSET,
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kNIC_REG_WRITE_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_WRITE_QOS_OFFSET,
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kNIC_REG_WRITE_QOS_ENET1G_TX = NIC_ENET1G_TX_BASE + NIC_WRITE_QOS_OFFSET,
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kNIC_REG_WRITE_QOS_ENET = NIC_ENET_BASE + NIC_WRITE_QOS_OFFSET,
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kNIC_REG_WRITE_QOS_USBO2 = NIC_USBO2_BASE + NIC_WRITE_QOS_OFFSET,
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kNIC_REG_WRITE_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_WRITE_QOS_OFFSET,
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kNIC_REG_WRITE_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_WRITE_QOS_OFFSET,
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kNIC_REG_WRITE_QOS_ENET_QOS = NIC_ENET_QOS_BASE + NIC_WRITE_QOS_OFFSET,
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kNIC_REG_WRITE_QOS_CM7 = NIC_CM7_BASE + NIC_WRITE_QOS_OFFSET,
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kNIC_REG_WRITE_QOS_DMA = NIC_DMA_BASE + NIC_WRITE_QOS_OFFSET,
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kNIC_REG_WRITE_QOS_IEE = NIC_IEE_BASE + NIC_WRITE_QOS_OFFSET,
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/* fn_mod */
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kNIC_REG_FN_MOD_GC355 = NIC_GC355_BASE + NIC_FN_MOD_OFFSET,
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kNIC_REG_FN_MOD_PXP = NIC_PXP_BASE + NIC_FN_MOD_OFFSET,
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kNIC_REG_FN_MOD_LCDIF = NIC_LCDIF_BASE + NIC_FN_MOD_OFFSET,
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kNIC_REG_FN_MOD_LCDIFV2 = NIC_LCDIFV2_BASE + NIC_FN_MOD_OFFSET,
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kNIC_REG_FN_MOD_CSI = NIC_CSI_BASE + NIC_FN_MOD_OFFSET,
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kNIC_REG_FN_MOD_CAAM = NIC_CAAM_BASE + NIC_FN_MOD_OFFSET,
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kNIC_REG_FN_MOD_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_FN_MOD_OFFSET,
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kNIC_REG_FN_MOD_ENET1G_TX = NIC_ENET1G_TX_BASE + NIC_FN_MOD_OFFSET,
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kNIC_REG_FN_MOD_ENET = NIC_ENET_BASE + NIC_FN_MOD_OFFSET,
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kNIC_REG_FN_MOD_USBO2 = NIC_USBO2_BASE + NIC_FN_MOD_OFFSET,
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kNIC_REG_FN_MOD_USDHC1 = NIC_USDHC1_BASE + NIC_FN_MOD_OFFSET,
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kNIC_REG_FN_MOD_USDHC2 = NIC_USDHC2_BASE + NIC_FN_MOD_OFFSET,
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kNIC_REG_FN_MOD_ENET_QOS = NIC_ENET_QOS_BASE + NIC_FN_MOD_OFFSET,
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kNIC_REG_FN_MOD_CM7 = NIC_CM7_BASE + NIC_FN_MOD_OFFSET,
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kNIC_REG_FN_MOD_DMA = NIC_DMA_BASE + NIC_FN_MOD_OFFSET,
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kNIC_REG_FN_MOD_IEE = NIC_IEE_BASE + NIC_FN_MOD_OFFSET,
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/* fn_mod_ahb */
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kNIC_REG_FN_MOD_AHB_ENET = NIC_ENET_BASE + NIC_FN_MOD_AHB_OFFSET,
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kNIC_REG_FN_MOD_AHB_DMA = NIC_DMA_BASE + NIC_FN_MOD_AHB_OFFSET,
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/* wr_tidemark */
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kNIC_REG_WR_TIDEMARK_LPSRMIX_M = NIC_LPSRMIX_M_BASE + NIC_WR_TIDEMARK_OFFSET,
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} nic_reg_t;
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/* fn_mod_ahb */
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typedef enum _nic_fn_mod_ahb
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{
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kNIC_FN_MOD_AHB_RD_INCR_OVERRIDE = 0,
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kNIC_FN_MOD_AHB_WR_INCR_OVERRIDE,
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kNIC_FN_MOD_AHB_LOCK_OVERRIDE,
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} nic_fn_mod_ahb_t;
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/* fn_mod */
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typedef enum _nic_fn_mod
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{
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kNIC_FN_MOD_ReadIssue = 0,
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kNIC_FN_MOD_WriteIssue,
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} nic_fn_mod_t;
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/* read_qos/write_qos */
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typedef enum _nic_qos
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{
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kNIC_QOS_0 = 0,
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kNIC_QOS_1,
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kNIC_QOS_2,
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kNIC_QOS_3,
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kNIC_QOS_4,
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kNIC_QOS_5,
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kNIC_QOS_6,
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kNIC_QOS_7,
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kNIC_QOS_8,
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kNIC_QOS_9,
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kNIC_QOS_10,
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kNIC_QOS_11,
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kNIC_QOS_12,
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kNIC_QOS_13,
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kNIC_QOS_14,
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kNIC_QOS_15,
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} nic_qos_t;
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/*******************************************************************************
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* API
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif /* __cplusplus */
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/*!
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* @brief Set read_qos Value
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*
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* @param base Base address of GPV address
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* @param value Target value (0 - 15)
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*/
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static inline void NIC_SetReadQos(nic_reg_t base, nic_qos_t value)
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{
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*(volatile uint32_t *)(base + NIC_READ_QOS_OFFSET) = (value & NIC_QOS_MASK);
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__DSB();
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}
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/*!
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* @brief Get read_qos Value
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*
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* @param base Base address of GPV address
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* @return Current value configured
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*/
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static inline nic_qos_t NIC_GetReadQos(nic_reg_t base)
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{
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return (nic_qos_t)((*(volatile uint32_t *)(base + NIC_READ_QOS_OFFSET)) & NIC_QOS_MASK);
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}
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/*!
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* @brief Set write_qos Value
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*
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* @param base Base address of GPV address
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* @param value Target value (0 - 15)
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*/
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static void inline NIC_SetWriteQos(nic_reg_t base, nic_qos_t value)
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{
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*(volatile uint32_t *)(base + NIC_WRITE_QOS_OFFSET) = (value & NIC_QOS_MASK);
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__DSB();
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}
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/*!
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* @brief Get write_qos Value
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*
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* @param base Base address of GPV address
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* @return Current value configured
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*/
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static inline nic_qos_t NIC_GetWriteQos(nic_reg_t base)
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{
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return (nic_qos_t)((*(volatile uint32_t *)(base + NIC_WRITE_QOS_OFFSET)) & NIC_QOS_MASK);
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}
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/*!
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* @brief Set fn_mod_ahb Value
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*
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* @param base Base address of GPV address
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* @param value Target value
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*/
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static inline void NIC_SetFnModAhb(nic_reg_t base, nic_fn_mod_ahb_t v)
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{
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*(volatile uint32_t *)(base + NIC_FN_MOD_AHB_OFFSET) = v;
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__DSB();
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}
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/*!
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* @brief Get fn_mod_ahb Value
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*
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* @param base Base address of GPV address
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* @return Current value configured
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*/
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static inline nic_fn_mod_ahb_t NIC_GetFnModAhb(nic_reg_t base)
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{
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return (nic_fn_mod_ahb_t)((*(volatile uint32_t *)(base + NIC_FN_MOD_AHB_OFFSET)) & NIC_FN_MOD_AHB_MASK);
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}
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/*!
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* @brief Set wr_tidemark Value
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*
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* @param base Base address of GPV address
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* @param value Target value (0 - 15)
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*/
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static inline void NIC_SetWrTideMark(nic_reg_t base, uint8_t value)
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{
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*(volatile uint32_t *)(base + NIC_WR_TIDEMARK_OFFSET) = (value & NIC_WR_TIDEMARK_MASK);
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__DSB();
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}
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/*!
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* @brief Get wr_tidemark Value
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*
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* @param base Base address of GPV address
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* @return Current value configured
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*/
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static inline uint8_t NIC_GetWrTideMark(nic_reg_t base)
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{
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return (uint8_t)((*(volatile uint32_t *)(base + NIC_WR_TIDEMARK_OFFSET)) & NIC_WR_TIDEMARK_MASK);
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}
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/*!
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* @brief Set fn_mod Value
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*
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* @param base Base address of GPV address
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* @param value Target value
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*/
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static inline void NIC_SetFnMod(nic_reg_t base, nic_fn_mod_t value)
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{
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*(volatile uint32_t *)(base + NIC_FN_MOD_OFFSET) = value;
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__DSB();
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}
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/*!
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* @brief Get fn_mod Value
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*
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* @param base Base address of GPV address
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* @return Current value configured
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*/
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static inline nic_fn_mod_t NIC_GetFnMod(nic_reg_t base)
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{
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return (nic_fn_mod_t)((*(volatile uint32_t *)(base + NIC_FN_MOD_OFFSET)) & NIC_FN_MOD_MASK);
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}
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#if defined(__cplusplus)
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}
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#endif /* __cplusplus */
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#endif /* _FSL_NIC301_H_ */
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