468 lines
14 KiB
C
468 lines
14 KiB
C
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/*
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* File : davinci_emac.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2013-01-30 weety first version
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*/
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#ifndef _DAVINCI_EMAC_H
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#define _DAVINCI_EMAC_H
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#include <mii.h>
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#ifndef NET_IP_ALIGN
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#define NET_IP_ALIGN 2
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#endif
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enum {
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EMAC_VERSION_1, /* DM644x */
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EMAC_VERSION_2, /* DM646x */
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};
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#define __iomem
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#define BIT(nr) (1UL << (nr))
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/* Configuration items */
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#define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC upto frames */
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#define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */
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#define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */
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#define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */
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#define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */
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#define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */
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#define EMAC_DEF_PROM_EN (0) /* Promiscous disabled */
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#define EMAC_DEF_PROM_CH (0) /* Promiscous channel is 0 */
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#define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */
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#define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */
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#define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */
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#define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */
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#define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */
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#define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/
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#define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */
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#define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */
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#define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
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#define EMAC_DEF_TX_CH (0) /* Default 0th channel */
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#define EMAC_DEF_RX_CH (0) /* Default 0th channel */
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#define EMAC_DEF_MDIO_TICK_MS (10) /* typically 1 tick=1 ms) */
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#define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */
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#define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */
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#define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */
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/* Buffer descriptor parameters */
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#define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */
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#define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */
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/* EMAC register related defines */
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#define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF)
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#define EMAC_NUM_MULTICAST_BITS (64)
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#define EMAC_TEARDOWN_VALUE (0xFFFFFFFC)
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#define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1)
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#define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1)
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#define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2)
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#define EMAC_RX_UNICAST_CLEAR_ALL (0xFF)
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#define EMAC_INT_MASK_CLEAR (0xFF)
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/* RX MBP register bit positions */
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#define EMAC_RXMBP_PASSCRC_MASK BIT(30)
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#define EMAC_RXMBP_QOSEN_MASK BIT(29)
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#define EMAC_RXMBP_NOCHAIN_MASK BIT(28)
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#define EMAC_RXMBP_CMFEN_MASK BIT(24)
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#define EMAC_RXMBP_CSFEN_MASK BIT(23)
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#define EMAC_RXMBP_CEFEN_MASK BIT(22)
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#define EMAC_RXMBP_CAFEN_MASK BIT(21)
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#define EMAC_RXMBP_PROMCH_SHIFT (16)
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#define EMAC_RXMBP_PROMCH_MASK (0x7 << 16)
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#define EMAC_RXMBP_BROADEN_MASK BIT(13)
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#define EMAC_RXMBP_BROADCH_SHIFT (8)
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#define EMAC_RXMBP_BROADCH_MASK (0x7 << 8)
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#define EMAC_RXMBP_MULTIEN_MASK BIT(5)
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#define EMAC_RXMBP_MULTICH_SHIFT (0)
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#define EMAC_RXMBP_MULTICH_MASK (0x7)
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#define EMAC_RXMBP_CHMASK (0x7)
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/* EMAC register definitions/bit maps used */
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# define EMAC_MBP_RXPROMISC (0x00200000)
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# define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16)
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# define EMAC_MBP_RXBCAST (0x00002000)
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# define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8)
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# define EMAC_MBP_RXMCAST (0x00000020)
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# define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7)
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/* EMAC mac_control register */
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#define EMAC_MACCONTROL_TXPTYPE BIT(9)
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#define EMAC_MACCONTROL_TXPACEEN BIT(6)
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#define EMAC_MACCONTROL_GMIIEN BIT(5)
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#define EMAC_MACCONTROL_GIGABITEN BIT(7)
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#define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0)
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#define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15)
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/* GIGABIT MODE related bits */
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#define EMAC_DM646X_MACCONTORL_GIG BIT(7)
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#define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
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/* EMAC mac_status register */
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#define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000)
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#define EMAC_MACSTATUS_TXERRCODE_SHIFT (20)
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#define EMAC_MACSTATUS_TXERRCH_MASK (0x7)
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#define EMAC_MACSTATUS_TXERRCH_SHIFT (16)
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#define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000)
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#define EMAC_MACSTATUS_RXERRCODE_SHIFT (12)
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#define EMAC_MACSTATUS_RXERRCH_MASK (0x7)
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#define EMAC_MACSTATUS_RXERRCH_SHIFT (8)
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/* EMAC RX register masks */
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#define EMAC_RX_MAX_LEN_MASK (0xFFFF)
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#define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF)
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/* MAC_IN_VECTOR (0x180) register bit fields */
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#define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17)
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#define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16)
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#define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8)
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#define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0)
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/** NOTE:: For DM646x the IN_VECTOR has changed */
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#define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH)
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#define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH)
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#define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26)
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#define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27)
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/* CPPI bit positions */
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#define EMAC_CPPI_SOP_BIT BIT(31)
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#define EMAC_CPPI_EOP_BIT BIT(30)
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#define EMAC_CPPI_OWNERSHIP_BIT BIT(29)
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#define EMAC_CPPI_EOQ_BIT BIT(28)
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#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
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#define EMAC_CPPI_PASS_CRC_BIT BIT(26)
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#define EMAC_RX_BD_BUF_SIZE (0xFFFF)
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#define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */
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#define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF)
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/* Max hardware defines */
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#define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */
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#define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
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/* EMAC Peripheral Device Register Memory Layout structure */
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#define EMAC_TXIDVER 0x0
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#define EMAC_TXCONTROL 0x4
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#define EMAC_TXTEARDOWN 0x8
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#define EMAC_RXIDVER 0x10
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#define EMAC_RXCONTROL 0x14
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#define EMAC_RXTEARDOWN 0x18
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#define EMAC_TXINTSTATRAW 0x80
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#define EMAC_TXINTSTATMASKED 0x84
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#define EMAC_TXINTMASKSET 0x88
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#define EMAC_TXINTMASKCLEAR 0x8C
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#define EMAC_MACINVECTOR 0x90
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#define EMAC_DM646X_MACEOIVECTOR 0x94
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#define EMAC_RXINTSTATRAW 0xA0
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#define EMAC_RXINTSTATMASKED 0xA4
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#define EMAC_RXINTMASKSET 0xA8
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#define EMAC_RXINTMASKCLEAR 0xAC
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#define EMAC_MACINTSTATRAW 0xB0
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#define EMAC_MACINTSTATMASKED 0xB4
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#define EMAC_MACINTMASKSET 0xB8
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#define EMAC_MACINTMASKCLEAR 0xBC
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#define EMAC_RXMBPENABLE 0x100
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#define EMAC_RXUNICASTSET 0x104
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#define EMAC_RXUNICASTCLEAR 0x108
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#define EMAC_RXMAXLEN 0x10C
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#define EMAC_RXBUFFEROFFSET 0x110
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#define EMAC_RXFILTERLOWTHRESH 0x114
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#define EMAC_MACCONTROL 0x160
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#define EMAC_MACSTATUS 0x164
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#define EMAC_EMCONTROL 0x168
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#define EMAC_FIFOCONTROL 0x16C
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#define EMAC_MACCONFIG 0x170
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#define EMAC_SOFTRESET 0x174
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#define EMAC_MACSRCADDRLO 0x1D0
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#define EMAC_MACSRCADDRHI 0x1D4
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#define EMAC_MACHASH1 0x1D8
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#define EMAC_MACHASH2 0x1DC
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#define EMAC_MACADDRLO 0x500
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#define EMAC_MACADDRHI 0x504
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#define EMAC_MACINDEX 0x508
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/* EMAC HDP and Completion registors */
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#define EMAC_TXHDP(ch) (0x600 + (ch * 4))
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#define EMAC_RXHDP(ch) (0x620 + (ch * 4))
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#define EMAC_TXCP(ch) (0x640 + (ch * 4))
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#define EMAC_RXCP(ch) (0x660 + (ch * 4))
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/* EMAC statistics registers */
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#define EMAC_RXGOODFRAMES 0x200
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#define EMAC_RXBCASTFRAMES 0x204
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#define EMAC_RXMCASTFRAMES 0x208
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#define EMAC_RXPAUSEFRAMES 0x20C
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#define EMAC_RXCRCERRORS 0x210
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#define EMAC_RXALIGNCODEERRORS 0x214
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#define EMAC_RXOVERSIZED 0x218
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#define EMAC_RXJABBER 0x21C
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#define EMAC_RXUNDERSIZED 0x220
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#define EMAC_RXFRAGMENTS 0x224
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#define EMAC_RXFILTERED 0x228
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#define EMAC_RXQOSFILTERED 0x22C
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#define EMAC_RXOCTETS 0x230
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#define EMAC_TXGOODFRAMES 0x234
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#define EMAC_TXBCASTFRAMES 0x238
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#define EMAC_TXMCASTFRAMES 0x23C
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#define EMAC_TXPAUSEFRAMES 0x240
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#define EMAC_TXDEFERRED 0x244
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#define EMAC_TXCOLLISION 0x248
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#define EMAC_TXSINGLECOLL 0x24C
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#define EMAC_TXMULTICOLL 0x250
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#define EMAC_TXEXCESSIVECOLL 0x254
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#define EMAC_TXLATECOLL 0x258
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#define EMAC_TXUNDERRUN 0x25C
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#define EMAC_TXCARRIERSENSE 0x260
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#define EMAC_TXOCTETS 0x264
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#define EMAC_NETOCTETS 0x280
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#define EMAC_RXSOFOVERRUNS 0x284
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#define EMAC_RXMOFOVERRUNS 0x288
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#define EMAC_RXDMAOVERRUNS 0x28C
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/* EMAC DM644x control registers */
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#define EMAC_CTRL_EWCTL (0x4)
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#define EMAC_CTRL_EWINTTCNT (0x8)
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/* EMAC MDIO related */
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/* Mask & Control defines */
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#define MDIO_CONTROL_CLKDIV (0xFF)
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#define MDIO_CONTROL_ENABLE BIT(30)
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#define MDIO_USERACCESS_GO BIT(31)
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#define MDIO_USERACCESS_WRITE BIT(30)
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#define MDIO_USERACCESS_READ (0)
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#define MDIO_USERACCESS_REGADR (0x1F << 21)
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#define MDIO_USERACCESS_PHYADR (0x1F << 16)
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#define MDIO_USERACCESS_DATA (0xFFFF)
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#define MDIO_USERPHYSEL_LINKSEL BIT(7)
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#define MDIO_VER_MODID (0xFFFF << 16)
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#define MDIO_VER_REVMAJ (0xFF << 8)
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#define MDIO_VER_REVMIN (0xFF)
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#define MDIO_USERACCESS(inst) (0x80 + (inst * 8))
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#define MDIO_USERPHYSEL(inst) (0x84 + (inst * 8))
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#define MDIO_CONTROL (0x04)
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/* EMAC DM646X control module registers */
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#define EMAC_DM646X_CMRXINTEN (0x14)
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#define EMAC_DM646X_CMTXINTEN (0x18)
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/* EMAC EOI codes for C0 */
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#define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
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#define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
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/* EMAC Stats Clear Mask */
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#define EMAC_STATS_CLR_MASK (0xFFFFFFFF)
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/** net_buf_obj: EMAC network bufferdata structure
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*
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* EMAC network buffer data structure
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*/
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struct emac_netbufobj {
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void *buf_token;
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char *data_ptr;
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int length;
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};
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/** net_pkt_obj: EMAC network packet data structure
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*
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* EMAC network packet data structure - supports buffer list (for future)
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*/
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struct emac_netpktobj {
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void *pkt_token; /* data token may hold tx/rx chan id */
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struct emac_netbufobj *buf_list; /* array of network buffer objects */
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int num_bufs;
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int pkt_length;
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};
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/** emac_tx_bd: EMAC TX Buffer descriptor data structure
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*
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* EMAC TX Buffer descriptor data structure
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*/
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struct emac_tx_bd {
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int h_next;
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int buff_ptr;
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int off_b_len;
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int mode; /* SOP, EOP, ownership, EOQ, teardown,Qstarv, length */
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struct emac_tx_bd __iomem *next;
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void *buf_token;
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};
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/** emac_txch: EMAC TX Channel data structure
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*
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* EMAC TX Channel data structure
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*/
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struct emac_txch {
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/* Config related */
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rt_uint32_t num_bd;
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rt_uint32_t service_max;
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/* CPPI specific */
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rt_uint32_t alloc_size;
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void __iomem *bd_mem;
|
||
|
|
struct emac_tx_bd __iomem *bd_pool_head;
|
||
|
|
struct emac_tx_bd __iomem *active_queue_head;
|
||
|
|
struct emac_tx_bd __iomem *active_queue_tail;
|
||
|
|
struct emac_tx_bd __iomem *last_hw_bdprocessed;
|
||
|
|
rt_uint32_t queue_active;
|
||
|
|
rt_uint32_t teardown_pending;
|
||
|
|
rt_uint32_t *tx_complete;
|
||
|
|
|
||
|
|
/** statistics */
|
||
|
|
rt_uint32_t proc_count; /* TX: # of times emac_tx_bdproc is called */
|
||
|
|
rt_uint32_t mis_queued_packets;
|
||
|
|
rt_uint32_t queue_reinit;
|
||
|
|
rt_uint32_t end_of_queue_add;
|
||
|
|
rt_uint32_t out_of_tx_bd;
|
||
|
|
rt_uint32_t no_active_pkts; /* IRQ when there were no packets to process */
|
||
|
|
rt_uint32_t active_queue_count;
|
||
|
|
};
|
||
|
|
|
||
|
|
/** emac_rx_bd: EMAC RX Buffer descriptor data structure
|
||
|
|
*
|
||
|
|
* EMAC RX Buffer descriptor data structure
|
||
|
|
*/
|
||
|
|
struct emac_rx_bd {
|
||
|
|
int h_next;
|
||
|
|
int buff_ptr;
|
||
|
|
int off_b_len;
|
||
|
|
int mode;
|
||
|
|
struct emac_rx_bd __iomem *next;
|
||
|
|
void *data_ptr;
|
||
|
|
void *buf_token;
|
||
|
|
};
|
||
|
|
|
||
|
|
/** emac_rxch: EMAC RX Channel data structure
|
||
|
|
*
|
||
|
|
* EMAC RX Channel data structure
|
||
|
|
*/
|
||
|
|
struct emac_rxch {
|
||
|
|
/* configuration info */
|
||
|
|
rt_uint32_t num_bd;
|
||
|
|
rt_uint32_t service_max;
|
||
|
|
rt_uint32_t buf_size;
|
||
|
|
char mac_addr[6];
|
||
|
|
|
||
|
|
/** CPPI specific */
|
||
|
|
rt_uint32_t alloc_size;
|
||
|
|
void __iomem *bd_mem;
|
||
|
|
struct emac_rx_bd __iomem *bd_pool_head;
|
||
|
|
struct emac_rx_bd __iomem *active_queue_head;
|
||
|
|
struct emac_rx_bd __iomem *active_queue_tail;
|
||
|
|
rt_uint32_t queue_active;
|
||
|
|
rt_uint32_t teardown_pending;
|
||
|
|
|
||
|
|
/* packet and buffer objects */
|
||
|
|
struct emac_netpktobj pkt_queue;
|
||
|
|
struct emac_netbufobj buf_queue;
|
||
|
|
|
||
|
|
/** statistics */
|
||
|
|
rt_uint32_t proc_count; /* number of times emac_rx_bdproc is called */
|
||
|
|
rt_uint32_t processed_bd;
|
||
|
|
rt_uint32_t recycled_bd;
|
||
|
|
rt_uint32_t out_of_rx_bd;
|
||
|
|
rt_uint32_t out_of_rx_buffers;
|
||
|
|
rt_uint32_t queue_reinit;
|
||
|
|
rt_uint32_t end_of_queue_add;
|
||
|
|
rt_uint32_t end_of_queue;
|
||
|
|
rt_uint32_t mis_queued_packets;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct net_device_stats
|
||
|
|
{
|
||
|
|
unsigned long rx_packets; /* total packets received */
|
||
|
|
unsigned long tx_packets; /* total packets transmitted */
|
||
|
|
unsigned long rx_bytes; /* total bytes received */
|
||
|
|
unsigned long tx_bytes; /* total bytes transmitted */
|
||
|
|
unsigned long rx_errors; /* bad packets received */
|
||
|
|
unsigned long tx_errors; /* packet transmit problems */
|
||
|
|
unsigned long rx_dropped; /* no space in linux buffers */
|
||
|
|
unsigned long tx_dropped; /* no space available in linux */
|
||
|
|
unsigned long multicast; /* multicast packets received */
|
||
|
|
unsigned long collisions;
|
||
|
|
|
||
|
|
/* detailed rx_errors: */
|
||
|
|
unsigned long rx_length_errors;
|
||
|
|
unsigned long rx_over_errors; /* receiver ring buff overflow */
|
||
|
|
unsigned long rx_crc_errors; /* recved pkt with crc error */
|
||
|
|
unsigned long rx_frame_errors; /* recv'd frame alignment error */
|
||
|
|
unsigned long rx_fifo_errors; /* recv'r fifo overrun */
|
||
|
|
unsigned long rx_missed_errors; /* receiver missed packet */
|
||
|
|
|
||
|
|
/* detailed tx_errors */
|
||
|
|
unsigned long tx_aborted_errors;
|
||
|
|
unsigned long tx_carrier_errors;
|
||
|
|
unsigned long tx_fifo_errors;
|
||
|
|
unsigned long tx_heartbeat_errors;
|
||
|
|
unsigned long tx_window_errors;
|
||
|
|
|
||
|
|
/* for cslip etc */
|
||
|
|
unsigned long rx_compressed;
|
||
|
|
unsigned long tx_compressed;
|
||
|
|
};
|
||
|
|
|
||
|
|
|
||
|
|
/* emac_priv: EMAC private data structure
|
||
|
|
*
|
||
|
|
* EMAC adapter private data structure
|
||
|
|
*/
|
||
|
|
#define MAX_ADDR_LEN 6
|
||
|
|
|
||
|
|
struct emac_priv {
|
||
|
|
/* inherit from ethernet device */
|
||
|
|
struct eth_device parent;
|
||
|
|
|
||
|
|
/* interface address info. */
|
||
|
|
rt_uint8_t mac_addr[MAX_ADDR_LEN]; /* hw address */
|
||
|
|
unsigned short phy_addr;
|
||
|
|
|
||
|
|
struct rt_semaphore tx_lock;
|
||
|
|
struct rt_semaphore rx_lock;
|
||
|
|
void __iomem *remap_addr;
|
||
|
|
rt_uint32_t emac_base_phys;
|
||
|
|
void __iomem *emac_base;
|
||
|
|
void __iomem *ctrl_base;
|
||
|
|
void __iomem *emac_ctrl_ram;
|
||
|
|
void __iomem *mdio_base;
|
||
|
|
rt_uint32_t ctrl_ram_size;
|
||
|
|
rt_uint32_t hw_ram_addr;
|
||
|
|
struct emac_txch *txch[EMAC_DEF_MAX_TX_CH];
|
||
|
|
struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH];
|
||
|
|
rt_uint32_t link; /* 1=link on, 0=link off */
|
||
|
|
rt_uint32_t speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
|
||
|
|
rt_uint32_t duplex; /* Link duplex: 0=Half, 1=Full */
|
||
|
|
rt_uint32_t rx_buf_size;
|
||
|
|
rt_uint32_t isr_count;
|
||
|
|
rt_uint8_t rmii_en;
|
||
|
|
rt_uint8_t version;
|
||
|
|
struct net_device_stats net_dev_stats;
|
||
|
|
rt_uint32_t mac_hash1;
|
||
|
|
rt_uint32_t mac_hash2;
|
||
|
|
rt_uint32_t multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
|
||
|
|
rt_uint32_t rx_addr_type;
|
||
|
|
/* periodic timer required for MDIO polling */
|
||
|
|
struct rt_timer timer;
|
||
|
|
rt_uint32_t periodic_ticks;
|
||
|
|
rt_uint32_t timer_active;
|
||
|
|
rt_uint32_t phy_mask;
|
||
|
|
/* mii_bus,phy members */
|
||
|
|
struct rt_semaphore lock;
|
||
|
|
};
|
||
|
|
|
||
|
|
|
||
|
|
#endif /* _DAVINCI_EMAC_H */
|
||
|
|
|