153 lines
7.3 KiB
C
153 lines
7.3 KiB
C
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////////////////////////////////////////////////////////////////////////////////
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/// @file reg_crs.h
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/// @author AE TEAM
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/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
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/// MM32 FIRMWARE LIBRARY.
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////////////////////////////////////////////////////////////////////////////////
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/// @attention
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///
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/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
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/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
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/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
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/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
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/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
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/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
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///
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/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
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////////////////////////////////////////////////////////////////////////////////
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// Define to prevent recursive inclusion
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#ifndef __REG_CRS_H
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#define __REG_CRS_H
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// Files includes
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#include <stdint.h>
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#include <stdbool.h>
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#include "types.h"
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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////////////////////////////////////////////////////////////////////////////////
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/// @brief CRS Base Address Definition
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////////////////////////////////////////////////////////////////////////////////
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#define CRS_BASE (APB1PERIPH_BASE + 0x6C00) ///< Base Address: 0x40006C00
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////////////////////////////////////////////////////////////////////////////////
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/// @brief CRS Register Structure Definition
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////////////////////////////////////////////////////////////////////////////////
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typedef struct {
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__IO u32 CR; ///< Control Register offset: 0x00
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__IO u32 CFGR; ///< Configuration Register offset: 0x04
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__IO u32 ISR; ///< Interrupt and Status Register offset: 0x08
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__IO u32 ICR; ///< Interrupt Flag Clear Register offset: 0x0C
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} CRS_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief CRS type pointer Definition
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////////////////////////////////////////////////////////////////////////////////
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#define CRS ((CRS_TypeDef*) CRS_BASE)
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////////////////////////////////////////////////////////////////////////////////
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/// @brief CRS_CR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define CRS_CR_OKIE_Pos (0)
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#define CRS_CR_OKIE (0x01U << CRS_CR_OKIE_Pos) ///< SYNC event OK interrupt enable
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#define CRS_CR_WARNIE_Pos (1)
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#define CRS_CR_WARNIE (0x01U << CRS_CR_WARNIE_Pos) ///< SYNC warning interrupt enable
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#define CRS_CR_ERRIE_Pos (2)
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#define CRS_CR_ERRIE (0x01U << CRS_CR_ERRIE_Pos) ///< Synchronization or trimming error interrupt enable
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#define CRS_CR_EXPTIE_Pos (3)
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#define CRS_CR_EXPTIE (0x01U << CRS_CR_EXPTIE_Pos) ///< Expected SYNC interrupt enable
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#define CRS_CR_CNTEN_Pos (5)
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#define CRS_CR_CNTEN (0x01U << CRS_CR_CNTEN_Pos) ///< Frequency error counter enable
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#define CRS_CR_AUTOTRIMEN_Pos (6)
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#define CRS_CR_AUTOTRIMEN (0x01U << CRS_CR_AUTOTRIMEN_Pos) ///< Automatic trimming enable
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#define CRS_CR_SWSYNC_Pos (7)
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#define CRS_CR_SWSYNC (0x01U << CRS_CR_SWSYNC_Pos) ///< Generate software SYNC event
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#define CRS_CR_TRIM_Pos (8)
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#define CRS_CR_TRIM (0x3FFU << CRS_CR_TRIM_Pos) ///< HSI 48 oscillator smooth trimming
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////////////////////////////////////////////////////////////////////////////////
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/// @brief CRS_CFGR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define CRS_CFGR_RELOAD_Pos (0)
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#define CRS_CFGR_RELOAD (0xFFFFU << CRS_CFGR_RELOAD_Pos) ///< Counter reload value
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#define CRS_CFGR_FELIM_Pos (16)
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#define CRS_CFGR_FELIM (0xFFU << CRS_CFGR_FELIM_Pos) ///< Frequency error limit
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#define CRS_CFGR_DIV_Pos (24)
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#define CRS_CFGR_DIV (0x07U << CRS_CFGR_DIV_Pos) ///< SYNC divider
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#define CRS_CFGR_SRC_Pos (28)
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#define CRS_CFGR_SRC (0x03U << CRS_CFGR_SRC_Pos) ///< SYNC signal source selection
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#define CRS_CFGR_SRC_MCO (0x00U << CRS_CFGR_SRC_Pos)
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#define CRS_CFGR_SRC_USBSOF (0x02U << CRS_CFGR_SRC_Pos)
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#define CRS_CFGR_POL_Pos (31)
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#define CRS_CFGR_POL (0x01U << CRS_CFGR_POL_Pos) ///< SYNC polarity selection
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////////////////////////////////////////////////////////////////////////////////
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/// @brief CRS_ISR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define CRS_ISR_OKIF_Pos (0)
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#define CRS_ISR_OKIF (0x01U << CRS_ISR_OKIF_Pos) ///< SYNC event OK flag
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#define CRS_ISR_WARNIF_Pos (1)
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#define CRS_ISR_WARNIF (0x01U << CRS_ISR_WARNIF_Pos) ///< SYNC warning flag
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#define CRS_ISR_ERRIF_Pos (2)
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#define CRS_ISR_ERRIF (0x01U << CRS_ISR_ERRIF_Pos) ///< Error flag
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#define CRS_ISR_EXPTIF_Pos (3)
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#define CRS_ISR_EXPTIF (0x01U << CRS_ISR_EXPTIF_Pos) ///< Expected SYNC flag
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#define CRS_ISR_ERR_Pos (8)
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#define CRS_ISR_ERR (0x01U << CRS_ISR_ERR_Pos) ///< SYNC error
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#define CRS_ISR_MISS_Pos (9)
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#define CRS_ISR_MISS (0x01U << CRS_ISR_MISS_Pos) ///< SYNC missed
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#define CRS_ISR_OVERFLOW_Pos (10)
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#define CRS_ISR_OVERFLOW (0x01U << CRS_ISR_OVERFLOW_Pos) ///< Trimming overflow or underflow
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#define CRS_ISR_FEDIR_Pos (15)
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#define CRS_ISR_FEDIR (0x01U << CRS_ISR_FEDIR_Pos) ///< Frequency error direction
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#define CRS_ISR_FECAP_Pos (16)
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#define CRS_ISR_FECAP (0xFFFFU << CRS_ISR_FECAP_Pos) ///< Frequency error capture
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////////////////////////////////////////////////////////////////////////////////
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/// @brief CRS_ICR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define CRS_ICR_OK_Pos (0)
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#define CRS_ICR_OK (0x01U << CRS_ICR_OK_Pos) ///< SYNC event OK clear flag
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#define CRS_ICR_WARN_Pos (1)
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#define CRS_ICR_WARN (0x01U << CRS_ICR_WARN_Pos) ///< SYNC warning clear flag
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#define CRS_ICR_ERR_Pos (2)
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#define CRS_ICR_ERR (0x01U << CRS_ICR_ERR_Pos) ///< Error clear flag
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#define CRS_ICR_EXPT_Pos (3)
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#define CRS_ICR_EXPT (0x01U << CRS_ICR_EXPT_Pos) ///< Expected SYNC clear flag
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/// @}
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/// @}
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/// @}
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////////////////////////////////////////////////////////////////////////////////
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#endif
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////////////////////////////////////////////////////////////////////////////////
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