246 lines
8.6 KiB
C
246 lines
8.6 KiB
C
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-03-18 luobeihai first version
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*/
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#include <board.h>
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#ifdef BSP_USING_SDRAM
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#include "drv_sdram.h"
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#define DRV_DEBUG
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#define LOG_TAG "drv.sdram"
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#include <drv_log.h>
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/* SDRAM GPIO Clock */
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#define RCM_SDRAM_GPIO_PERIPH (RCM_AHB1_PERIPH_GPIOA | \
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RCM_AHB1_PERIPH_GPIOD | \
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RCM_AHB1_PERIPH_GPIOF | \
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RCM_AHB1_PERIPH_GPIOG | \
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RCM_AHB1_PERIPH_GPIOH | \
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RCM_AHB1_PERIPH_GPIOI )
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#ifdef RT_USING_MEMHEAP_AS_HEAP
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static struct rt_memheap system_heap;
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#endif
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/**
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* @brief sdram gpio init
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* @param None
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* @retval None
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*/
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static void SDRAM_GPIO_Init(void)
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{
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GPIO_Config_T gpioConfig;
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RCM_EnableAHB1PeriphClock(RCM_SDRAM_GPIO_PERIPH);
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gpioConfig.speed = GPIO_SPEED_50MHz;
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gpioConfig.mode = GPIO_MODE_AF;
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gpioConfig.otype = GPIO_OTYPE_PP;
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gpioConfig.pupd = GPIO_PUPD_NOPULL;
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gpioConfig.pin = GPIO_PIN_10 | GPIO_PIN_12 |
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GPIO_PIN_13 | GPIO_PIN_14 |
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GPIO_PIN_15;
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GPIO_Config(GPIOD, &gpioConfig);
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GPIO_ConfigPinAF(GPIOD, GPIO_PIN_SOURCE_10, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOD, GPIO_PIN_SOURCE_12, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOD, GPIO_PIN_SOURCE_13, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOD, GPIO_PIN_SOURCE_14, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOD, GPIO_PIN_SOURCE_15, GPIO_AF_FSMC);
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gpioConfig.pin = GPIO_PIN_0 | GPIO_PIN_1 |
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GPIO_PIN_2 | GPIO_PIN_3 |
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GPIO_PIN_4 | GPIO_PIN_6 |
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GPIO_PIN_7 | GPIO_PIN_8 |
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GPIO_PIN_9 | GPIO_PIN_10 |
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GPIO_PIN_11;
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GPIO_Config(GPIOF, &gpioConfig);
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GPIO_ConfigPinAF(GPIOF, GPIO_PIN_SOURCE_0, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOF, GPIO_PIN_SOURCE_1, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOF, GPIO_PIN_SOURCE_2, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOF, GPIO_PIN_SOURCE_3, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOF, GPIO_PIN_SOURCE_4, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOF, GPIO_PIN_SOURCE_6, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOF, GPIO_PIN_SOURCE_7, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOF, GPIO_PIN_SOURCE_8, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOF, GPIO_PIN_SOURCE_9, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOF, GPIO_PIN_SOURCE_10, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOF, GPIO_PIN_SOURCE_11, GPIO_AF_FSMC);
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gpioConfig.pin = GPIO_PIN_1 | GPIO_PIN_2 |
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GPIO_PIN_3 | GPIO_PIN_4 |
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GPIO_PIN_5 | GPIO_PIN_6 |
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GPIO_PIN_8 | GPIO_PIN_15;
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GPIO_Config(GPIOG, &gpioConfig);
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GPIO_ConfigPinAF(GPIOG, GPIO_PIN_SOURCE_1, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOG, GPIO_PIN_SOURCE_2, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOG, GPIO_PIN_SOURCE_3, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOG, GPIO_PIN_SOURCE_4, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOG, GPIO_PIN_SOURCE_5, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOG, GPIO_PIN_SOURCE_6, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOG, GPIO_PIN_SOURCE_8, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOG, GPIO_PIN_SOURCE_15, GPIO_AF_FSMC);
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gpioConfig.pin = GPIO_PIN_3 | GPIO_PIN_5 |
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GPIO_PIN_8 | GPIO_PIN_10 |
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GPIO_PIN_13 | GPIO_PIN_15;
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GPIO_Config(GPIOH, &gpioConfig);
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GPIO_ConfigPinAF(GPIOH, GPIO_PIN_SOURCE_3, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOH, GPIO_PIN_SOURCE_5, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOH, GPIO_PIN_SOURCE_8, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOH, GPIO_PIN_SOURCE_10, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOH, GPIO_PIN_SOURCE_13, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOH, GPIO_PIN_SOURCE_15, GPIO_AF_FSMC);
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gpioConfig.pin = GPIO_PIN_3 | GPIO_PIN_7 |
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GPIO_PIN_8 | GPIO_PIN_9 |
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GPIO_PIN_10 | GPIO_PIN_11;
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GPIO_Config(GPIOI, &gpioConfig);
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GPIO_ConfigPinAF(GPIOI, GPIO_PIN_SOURCE_3, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOI, GPIO_PIN_SOURCE_7, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOI, GPIO_PIN_SOURCE_8, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOI, GPIO_PIN_SOURCE_9, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOI, GPIO_PIN_SOURCE_10, GPIO_AF_FSMC);
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GPIO_ConfigPinAF(GPIOI, GPIO_PIN_SOURCE_11, GPIO_AF_FSMC);
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}
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static int SDRAM_Init(void)
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{
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int result = RT_EOK;
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DMC_Config_T dmc_init_config;
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DMC_TimingConfig_T dmc_timing_config;
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/* Config the SDRAM clock prescaler */
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RCM_ConfigSDRAM(RCM_SDRAM_DIV_4);
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/* enable sdram clock */
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RCM->AHB3CLKEN |= BIT0;
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/* sdram gpio init */
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SDRAM_GPIO_Init();
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/* dmc timing config */
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dmc_timing_config.latencyCAS = DMC_CAS_LATENCY_3; //!< Configure CAS latency period
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dmc_timing_config.tARP = DMC_AUTO_REFRESH_10; //!< Configure auto refresh period
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dmc_timing_config.tRAS = DMC_RAS_MINIMUM_2; //!< Configure line activation and precharging minimum time
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dmc_timing_config.tCMD = DMC_ATA_CMD_1; //!< Configure active to active period
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dmc_timing_config.tRCD = DMC_DELAY_TIME_1; //!< Configure RAS To CAS delay Time
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dmc_timing_config.tRP = DMC_PRECHARGE_1; //!< Configure precharge period
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dmc_timing_config.tWR = DMC_NEXT_PRECHARGE_2; //!< Configure time between the Last Data and The Next Precharge for write
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dmc_timing_config.tXSR = 3; //!< Configure XSR0
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dmc_timing_config.tRFP = 0x2F9; //!< Configure refresh Cycle
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#if SDRAM_TARGET_BANK == 1
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dmc_init_config.bankWidth = DMC_BANK_WIDTH_1; //!< Configure bank address width
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#else
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dmc_init_config.bankWidth = DMC_BANK_WIDTH_2; //!< Configure bank address width
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#endif
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dmc_init_config.clkPhase = DMC_CLK_PHASE_REVERSE; //!< Configure clock phase
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dmc_init_config.rowWidth = SDRAM_ROW_BITS; //!< Configure row address width
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dmc_init_config.colWidth = SDRAM_COLUMN_BITS; //!< Configure column address width
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dmc_init_config.timing = dmc_timing_config;
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DMC_Config(&dmc_init_config);
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DMC_ConfigOpenBank(DMC_BANK_NUMBER_2);
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DMC_EnableAccelerateModule();
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DMC_Enable();
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LOG_D("sdram init success, mapped at 0x%X, size is %d bytes, data width is %d", SDRAM_BANK_ADDR, SDRAM_SIZE, SDRAM_DATA_WIDTH);
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#ifdef RT_USING_MEMHEAP_AS_HEAP
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/* If RT_USING_MEMHEAP_AS_HEAP is enabled, SDRAM is initialized to the heap */
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rt_memheap_init(&system_heap, "sdram", (void *)SDRAM_BANK_ADDR, SDRAM_SIZE);
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#endif
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return result;
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}
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INIT_BOARD_EXPORT(SDRAM_Init);
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#ifdef DRV_DEBUG
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#ifdef FINSH_USING_MSH
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int sdram_test(void)
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{
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int i = 0;
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uint32_t start_time = 0, time_cast = 0;
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#if SDRAM_DATA_WIDTH == 8
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char data_width = 1;
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uint8_t data = 0;
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#elif SDRAM_DATA_WIDTH == 16
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char data_width = 2;
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uint16_t data = 0;
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#else
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char data_width = 4;
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uint32_t data = 0;
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#endif
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/* write data */
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LOG_D("Writing the %ld bytes data, waiting....", SDRAM_SIZE);
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start_time = rt_tick_get();
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for (i = 0; i < SDRAM_SIZE / data_width; i++)
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{
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#if SDRAM_DATA_WIDTH == 8
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*(__IO uint8_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint8_t)(i % 100);
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#elif SDRAM_DATA_WIDTH == 16
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*(__IO uint16_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint16_t)(i % 1000);
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#else
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*(__IO uint32_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint32_t)(i % 1000);
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#endif
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}
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time_cast = rt_tick_get() - start_time;
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LOG_D("Write data success, total time: %d.%03dS.", time_cast / RT_TICK_PER_SECOND,
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time_cast % RT_TICK_PER_SECOND / ((RT_TICK_PER_SECOND * 1 + 999) / 1000));
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/* read data */
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LOG_D("start Reading and verifying data, waiting....");
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for (i = 0; i < SDRAM_SIZE / data_width; i++)
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{
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#if SDRAM_DATA_WIDTH == 8
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data = *(__IO uint8_t *)(SDRAM_BANK_ADDR + i * data_width);
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if (data != i % 100)
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{
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LOG_E("SDRAM test failed!");
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break;
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}
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#elif SDRAM_DATA_WIDTH == 16
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data = *(__IO uint16_t *)(SDRAM_BANK_ADDR + i * data_width);
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if (data != i % 1000)
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{
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LOG_E("SDRAM test failed!");
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break;
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}
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#else
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data = *(__IO uint32_t *)(SDRAM_BANK_ADDR + i * data_width);
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if (data != i % 1000)
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{
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LOG_E("SDRAM test failed!");
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break;
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}
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#endif
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}
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if (i >= SDRAM_SIZE / data_width)
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{
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LOG_D("SDRAM test success!");
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}
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return RT_EOK;
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}
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MSH_CMD_EXPORT(sdram_test, sdram test)
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#endif /* FINSH_USING_MSH */
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#endif /* DRV_DEBUG */
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#endif /* BSP_USING_SDRAM */
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