298 lines
9.9 KiB
C
298 lines
9.9 KiB
C
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/*
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******************************************************************************
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* @file HAL_DMA.h
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* @version V1.0.0
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* @date 2020
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* @brief Header file of DMA HAL module.
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******************************************************************************
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*/
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#ifndef __HAL_DMA_H__
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#define __HAL_DMA_H__
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#include "ACM32Fxx_HAL.h"
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#define DMA_CHANNEL_NUM (8)
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/******************************************************************************/
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/* Peripheral Registers Bits Definition */
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/******************************************************************************/
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/**************** Bit definition for DMA CONFIG register ***********************/
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#define DMA_CONFIG_M2ENDIAN BIT2
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#define DMA_CONFIG_M1ENDIAN BIT1
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#define DMA_CONFIG_EN BIT0
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/**************** Bit definition for DMA Channel CTRL register ***********************/
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#define DMA_CHANNEL_CTRL_ITC BIT31
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#define DMA_CHANNEL_CTRL_DI BIT27
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#define DMA_CHANNEL_CTRL_SI BIT26
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/**************** Bit definition for DMA Channel CONFIG register ***********************/
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#define DMA_CHANNEL_CONFIG_DEST_PERIPH (BIT19|BIT20|BIT21|BIT22|BIT23|BIT24)
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#define DMA_CHANNEL_CONFIG_DEST_PERIPH_POS (19)
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#define DMA_CHANNEL_CONFIG_HALT BIT18
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#define DMA_CHANNEL_CONFIG_ACTIVE BIT17
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#define DMA_CHANNEL_CONFIG_LOCK BIT16
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#define DMA_CHANNEL_CONFIG_ITC BIT15
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#define DMA_CHANNEL_CONFIG_IE BIT14
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#define DMA_CHANNEL_CONFIG_FLOW_CTRL (BIT11|BIT12|BIT13)
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#define DMA_CHANNEL_CONFIG_SRC_PERIPH (BIT1|BIT2|BIT3|BIT4|BIT5|BIT6)
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#define DMA_CHANNEL_CONFIG_SRC_PERIPH_POS (1)
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#define DMA_CHANNEL_CONFIG_EN BIT0
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/** @defgroup DMA_DATA_FLOW
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* @{
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*/
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#define DMA_DATA_FLOW_M2M (0x00000000)
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#define DMA_DATA_FLOW_M2P (0x00000800)
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#define DMA_DATA_FLOW_P2M (0x00001000)
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/**
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* @}
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*/
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/** @defgroup REQUEST_ID
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* @{
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*/
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#define REG_M2M (0)
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#define REQ0_ADC (0)
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#define REQ1_SPI1_SEND (1)
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#define REQ2_SPI1_RECV (2)
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#define REQ3_SPI2_SEND (3)
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#define REQ4_SPI2_RECV (4)
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#define REQ5_UART1_SEND (5)
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#define REQ6_UART1_RECV (6)
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#define REQ7_UART2_SEND (7)
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#define REQ8_UART2_RECV (8)
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#define REQ9_I2C1_SEND (9)
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#define REQ10_I2C1_RECV (10)
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#define REQ11_I2C2_SEND (11)
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#define REQ12_I2C2_RECV (12)
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#define REQ13_TIM1_CH1 (13)
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#define REQ14_TIM1_CH2 (14)
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#define REQ15_TIM1_CH3 (15)
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#define REQ16_TIM1_CH4 (16)
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#define REQ17_TIM1_UP (17)
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#define REQ18_TIM1_TRIG_COM (18)
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#define REQ19_TIM3_CH3 (19)
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#define REQ20_TIM3_CH4_OR_UP (20)
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#define REQ21_TIM3_CH1_OR_TRIG (21)
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#define REQ22_TIM3_CH2 (22)
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#define REQ23_TIM6_UP (23)
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#define REQ24_TIM15_CH1_UP_TRIG_COM (24)
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#define REQ25_TIM15_CH2 (25)
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#define REQ26_TIM16_CH1_UP (26)
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#define REQ27_TIM16_TRIG_COM (27)
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#define REQ27_UART3_SEND (27)
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#define REQ28_TIM17_CH1_UP (28)
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#define REQ29_TIM17_TRIG_COM (29)
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#define REQ29_UART3_RECV (29)
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#define REQ30_LPUART_SEND (30)
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#define REQ31_LPUART_RECV (31)
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#define REQ32_TIM2_CH3 (32)
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#define REQ33_TIM2_CH4 (33)
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#define REQ34_TIM2_CH1 (34)
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#define REQ35_TIM2_CH2 (35)
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#define REQ36_TIM7_UP (36)
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#define REQ37_I2S1_TX (37)
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#define REQ38_I2S1_RX (38)
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#define REQ39_DAC1_CH1 (39)
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#define REQ40_DAC1_CH2 (40)
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#define REQ41_TIM4_CH3 (41)
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#define REQ42_TIM4_CH4 (42)
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#define REQ43_TIM4_CH1 (43)
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#define REQ44_TIM4_CH2 (44)
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#define REQ45_UART4_SEND (45)
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#define REQ46_UART4_RECV (46)
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#define REQ47_SPI3_SEND (47)
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#define REQ48_SPI3_RECV (48)
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#define REQ49_SPI4_SEND (49)
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#define REQ50_SPI4_RECV (50)
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#define REQ_MAX_LIMIT (51)
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/**
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* @}
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*/
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/** @defgroup DMA_SOURCE_ADDR_INCREASE
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* @{
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*/
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#define DMA_SOURCE_ADDR_INCREASE_DISABLE (0x00000000)
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#define DMA_SOURCE_ADDR_INCREASE_ENABLE (0x04000000)
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/**
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* @}
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*/
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/** @defgroup DMA_DST_ADDR_INCREASE
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* @{
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*/
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#define DMA_DST_ADDR_INCREASE_DISABLE (0x00000000)
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#define DMA_DST_ADDR_INCREASE_ENABLE (0x08000000)
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/**
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* @}
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*/
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/** @defgroup DMA_SRC_WIDTH
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* @{
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*/
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#define DMA_SRC_WIDTH_BYTE (0x00000000) /* 8bit */
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#define DMA_SRC_WIDTH_HALF_WORD (0x00040000) /* 16bit */
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#define DMA_SRC_WIDTH_WORD (0x00080000) /* 36bit */
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/**
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* @}
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*/
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/** @defgroup DMA_DST_WIDTH
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* @{
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*/
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#define DMA_DST_WIDTH_BYTE (0x00000000) /* 8bit */
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#define DMA_DST_WIDTH_HALF_WORD (0x00200000) /* 16bit */
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#define DMA_DST_WIDTH_WORD (0x00400000) /* 36bit */
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/**
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* @}
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*/
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/** @defgroup DMA_MODE DMA MODE
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* @{
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*/
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#define DMA_NORMAL 0x00000000U /*!< Normal mode */
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#define DMA_CIRCULAR 0x00000001U /*!< Circular mode */
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/**
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* @}
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*/
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/**
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* @brief DMA burst length Structure definition
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*/
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typedef enum
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{
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DMA_BURST_LENGTH_1 = 0,
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DMA_BURST_LENGTH_4 = 1,
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DMA_BURST_LENGTH_8 = 2,
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DMA_BURST_LENGTH_16 = 3,
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DMA_BURST_LENGTH_32 = 4,
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DMA_BURST_LENGTH_64 = 5,
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DMA_BURST_LENGTH_128 = 6,
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DMA_BURST_LENGTH_256 = 7,
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}DMA_BURST_LENGTH;
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/**
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* @brief DMA Configuration Structure definition
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*/
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typedef struct
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{
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uint32_t Mode; /* This parameter can be a value of @ref DMA_MODE */
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uint32_t Data_Flow; /* This parameter can be a value of @ref DMA_DATA_FLOW */
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uint32_t Request_ID; /* This parameter can be a value of @ref REQUEST_ID */
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uint32_t Source_Inc; /* This parameter can be a value of @ref DMA_SOURCE_ADDR_INCREASE */
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uint32_t Desination_Inc; /* This parameter can be a value of @ref DMA_DST_ADDR_INCREASE */
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uint32_t Source_Width; /* This parameter can be a value of @ref DMA_SRC_WIDTH */
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uint32_t Desination_Width; /* This parameter can be a value of @ref DMA_DST_WIDTH */
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}DMA_InitParaTypeDef;
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/**
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* @brief DMA handle Structure definition
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*/
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typedef struct
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{
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DMA_Channel_TypeDef *Instance; /* DMA registers base address */
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DMA_InitParaTypeDef Init; /* DMA initialization parameters */
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void (*DMA_ITC_Callback)(void); /* DMA transfer complete callback */
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void (*DMA_IE_Callback)(void); /* DMA error complete callback */
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}DMA_HandleTypeDef;
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/**
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* @brief DMA Link List Item Structure
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*/
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typedef struct DMA_NextLink
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{
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uint32_t SrcAddr; /* source address */
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uint32_t DstAddr; /* desination address */
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struct DMA_NextLink *Next; /* Next Link */
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uint32_t Control; /* Control */
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}DMA_LLI_InitTypeDef;
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/** @defgroup GPIO Private Macros
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* @{
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*/
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#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
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((MODE) == DMA_CIRCULAR))
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#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA_Channel0) || \
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((INSTANCE) == DMA_Channel1) || \
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((INSTANCE) == DMA_Channel2) || \
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((INSTANCE) == DMA_Channel3) || \
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((INSTANCE) == DMA_Channel4) || \
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((INSTANCE) == DMA_Channel5) || \
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((INSTANCE) == DMA_Channel6) || \
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((INSTANCE) == DMA_Channel7))
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#define IS_DMA_DATA_FLOW(DATA_FLOW) (((DATA_FLOW) == DMA_DATA_FLOW_M2M) || \
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((DATA_FLOW) == DMA_DATA_FLOW_M2P) || \
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((DATA_FLOW) == DMA_DATA_FLOW_P2M))
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#define IS_DMA_REQUEST_ID(REQUEST_ID) ((REQUEST_ID < REQ_MAX_LIMIT) ? true : false)
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#define IS_DMA_SRC_WIDTH(WIDTH) (((WIDTH) == DMA_SRC_WIDTH_BYTE) || \
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((WIDTH) == DMA_SRC_WIDTH_HALF_WORD) || \
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((WIDTH) == DMA_SRC_WIDTH_WORD))
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#define IS_DMA_DST_WIDTH(WIDTH) (((WIDTH) == DMA_DST_WIDTH_BYTE) || \
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((WIDTH) == DMA_DST_WIDTH_HALF_WORD) || \
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((WIDTH) == DMA_DST_WIDTH_WORD))
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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#define __HAL_LINK_DMA(_HANDLE_, _DMA_LINK_, _DMA_HANDLE_) (_HANDLE_._DMA_LINK_ = &_DMA_HANDLE_)
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/* HAL_DMA_IRQHandler */
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void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
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/* HAL_DMA_Init */
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HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
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/* HAL_DMA_DeInit */
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HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
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/* HAL_DMA_Start */
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HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size);
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/* HAL_DMA_Start */
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HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size);
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/* HAL_DMA_Abort */
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HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
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/* HAL_DMA_GetState */
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HAL_StatusTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
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#endif
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