501 lines
16 KiB
C
501 lines
16 KiB
C
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/*
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* Copyright (c) 2014, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
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* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*/
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/*
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* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
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*
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* This file was generated automatically and any changes may be lost.
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*/
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#ifndef __HW_GPIO_REGISTERS_H__
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#define __HW_GPIO_REGISTERS_H__
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#include "regs.h"
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/*
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* MK64F12 GPIO
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*
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* General Purpose Input/Output
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*
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* Registers defined in this header file:
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* - HW_GPIO_PDOR - Port Data Output Register
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* - HW_GPIO_PSOR - Port Set Output Register
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* - HW_GPIO_PCOR - Port Clear Output Register
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* - HW_GPIO_PTOR - Port Toggle Output Register
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* - HW_GPIO_PDIR - Port Data Input Register
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* - HW_GPIO_PDDR - Port Data Direction Register
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*
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* - hw_gpio_t - Struct containing all module registers.
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*/
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//! @name Module base addresses
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//@{
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#ifndef REGS_GPIO_BASE
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#define HW_GPIO_INSTANCE_COUNT (5U) //!< Number of instances of the GPIO module.
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#define HW_GPIOA (0U) //!< Instance number for GPIOA.
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#define HW_GPIOB (1U) //!< Instance number for GPIOB.
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#define HW_GPIOC (2U) //!< Instance number for GPIOC.
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#define HW_GPIOD (3U) //!< Instance number for GPIOD.
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#define HW_GPIOE (4U) //!< Instance number for GPIOE.
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#define REGS_GPIOA_BASE (0x400FF000U) //!< Base address for GPIOA.
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#define REGS_GPIOB_BASE (0x400FF040U) //!< Base address for GPIOB.
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#define REGS_GPIOC_BASE (0x400FF080U) //!< Base address for GPIOC.
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#define REGS_GPIOD_BASE (0x400FF0C0U) //!< Base address for GPIOD.
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#define REGS_GPIOE_BASE (0x400FF100U) //!< Base address for GPIOE.
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//! @brief Table of base addresses for GPIO instances.
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static const uint32_t __g_regs_GPIO_base_addresses[] = {
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REGS_GPIOA_BASE,
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REGS_GPIOB_BASE,
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REGS_GPIOC_BASE,
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REGS_GPIOD_BASE,
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REGS_GPIOE_BASE,
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};
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//! @brief Get the base address of GPIO by instance number.
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//! @param x GPIO instance number, from 0 through 4.
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#define REGS_GPIO_BASE(x) (__g_regs_GPIO_base_addresses[(x)])
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//! @brief Get the instance number given a base address.
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//! @param b Base address for an instance of GPIO.
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#define REGS_GPIO_INSTANCE(b) ((b) == REGS_GPIOA_BASE ? HW_GPIOA : (b) == REGS_GPIOB_BASE ? HW_GPIOB : (b) == REGS_GPIOC_BASE ? HW_GPIOC : (b) == REGS_GPIOD_BASE ? HW_GPIOD : (b) == REGS_GPIOE_BASE ? HW_GPIOE : 0)
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_GPIO_PDOR - Port Data Output Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_GPIO_PDOR - Port Data Output Register (RW)
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*
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* Reset value: 0x00000000U
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*
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* This register configures the logic levels that are driven on each
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* general-purpose output pins. Do not modify pin configuration registers associated with
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* pins not available in your selected package. All unbonded pins not available in
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* your package will default to DISABLE state for lowest power consumption.
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*/
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typedef union _hw_gpio_pdor
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{
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uint32_t U;
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struct _hw_gpio_pdor_bitfields
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{
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uint32_t PDO : 32; //!< [31:0] Port Data Output
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} B;
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} hw_gpio_pdor_t;
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#endif
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/*!
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* @name Constants and macros for entire GPIO_PDOR register
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*/
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//@{
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#define HW_GPIO_PDOR_ADDR(x) (REGS_GPIO_BASE(x) + 0x0U)
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#ifndef __LANGUAGE_ASM__
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#define HW_GPIO_PDOR(x) (*(__IO hw_gpio_pdor_t *) HW_GPIO_PDOR_ADDR(x))
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#define HW_GPIO_PDOR_RD(x) (HW_GPIO_PDOR(x).U)
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#define HW_GPIO_PDOR_WR(x, v) (HW_GPIO_PDOR(x).U = (v))
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#define HW_GPIO_PDOR_SET(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) | (v)))
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#define HW_GPIO_PDOR_CLR(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) & ~(v)))
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#define HW_GPIO_PDOR_TOG(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) ^ (v)))
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#endif
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//@}
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/*
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* Constants & macros for individual GPIO_PDOR bitfields
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*/
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/*!
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* @name Register GPIO_PDOR, field PDO[31:0] (RW)
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*
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* Register bits for unbonded pins return a undefined value when read.
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*
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* Values:
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* - 0 - Logic level 0 is driven on pin, provided pin is configured for
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* general-purpose output.
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* - 1 - Logic level 1 is driven on pin, provided pin is configured for
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* general-purpose output.
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*/
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//@{
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#define BP_GPIO_PDOR_PDO (0U) //!< Bit position for GPIO_PDOR_PDO.
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#define BM_GPIO_PDOR_PDO (0xFFFFFFFFU) //!< Bit mask for GPIO_PDOR_PDO.
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#define BS_GPIO_PDOR_PDO (32U) //!< Bit field size in bits for GPIO_PDOR_PDO.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the GPIO_PDOR_PDO field.
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#define BR_GPIO_PDOR_PDO(x) (HW_GPIO_PDOR(x).U)
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#endif
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//! @brief Format value for bitfield GPIO_PDOR_PDO.
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#define BF_GPIO_PDOR_PDO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PDOR_PDO), uint32_t) & BM_GPIO_PDOR_PDO)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the PDO field to a new value.
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#define BW_GPIO_PDOR_PDO(x, v) (HW_GPIO_PDOR_WR(x, v))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_GPIO_PSOR - Port Set Output Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_GPIO_PSOR - Port Set Output Register (WORZ)
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*
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* Reset value: 0x00000000U
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*
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* This register configures whether to set the fields of the PDOR.
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*/
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typedef union _hw_gpio_psor
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{
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uint32_t U;
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struct _hw_gpio_psor_bitfields
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{
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uint32_t PTSO : 32; //!< [31:0] Port Set Output
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} B;
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} hw_gpio_psor_t;
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#endif
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/*!
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* @name Constants and macros for entire GPIO_PSOR register
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*/
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//@{
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#define HW_GPIO_PSOR_ADDR(x) (REGS_GPIO_BASE(x) + 0x4U)
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#ifndef __LANGUAGE_ASM__
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#define HW_GPIO_PSOR(x) (*(__O hw_gpio_psor_t *) HW_GPIO_PSOR_ADDR(x))
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#define HW_GPIO_PSOR_RD(x) (HW_GPIO_PSOR(x).U)
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#define HW_GPIO_PSOR_WR(x, v) (HW_GPIO_PSOR(x).U = (v))
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#endif
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//@}
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/*
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* Constants & macros for individual GPIO_PSOR bitfields
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*/
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/*!
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* @name Register GPIO_PSOR, field PTSO[31:0] (WORZ)
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*
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* Writing to this register will update the contents of the corresponding bit in
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* the PDOR as follows:
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*
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* Values:
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* - 0 - Corresponding bit in PDORn does not change.
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* - 1 - Corresponding bit in PDORn is set to logic 1.
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*/
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//@{
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#define BP_GPIO_PSOR_PTSO (0U) //!< Bit position for GPIO_PSOR_PTSO.
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#define BM_GPIO_PSOR_PTSO (0xFFFFFFFFU) //!< Bit mask for GPIO_PSOR_PTSO.
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#define BS_GPIO_PSOR_PTSO (32U) //!< Bit field size in bits for GPIO_PSOR_PTSO.
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//! @brief Format value for bitfield GPIO_PSOR_PTSO.
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#define BF_GPIO_PSOR_PTSO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PSOR_PTSO), uint32_t) & BM_GPIO_PSOR_PTSO)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the PTSO field to a new value.
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#define BW_GPIO_PSOR_PTSO(x, v) (HW_GPIO_PSOR_WR(x, v))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_GPIO_PCOR - Port Clear Output Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_GPIO_PCOR - Port Clear Output Register (WORZ)
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*
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* Reset value: 0x00000000U
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*
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* This register configures whether to clear the fields of PDOR.
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*/
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typedef union _hw_gpio_pcor
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{
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uint32_t U;
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struct _hw_gpio_pcor_bitfields
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{
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uint32_t PTCO : 32; //!< [31:0] Port Clear Output
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} B;
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} hw_gpio_pcor_t;
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#endif
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/*!
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* @name Constants and macros for entire GPIO_PCOR register
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*/
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//@{
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#define HW_GPIO_PCOR_ADDR(x) (REGS_GPIO_BASE(x) + 0x8U)
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#ifndef __LANGUAGE_ASM__
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#define HW_GPIO_PCOR(x) (*(__O hw_gpio_pcor_t *) HW_GPIO_PCOR_ADDR(x))
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#define HW_GPIO_PCOR_RD(x) (HW_GPIO_PCOR(x).U)
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#define HW_GPIO_PCOR_WR(x, v) (HW_GPIO_PCOR(x).U = (v))
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#endif
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//@}
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/*
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* Constants & macros for individual GPIO_PCOR bitfields
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*/
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/*!
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* @name Register GPIO_PCOR, field PTCO[31:0] (WORZ)
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*
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* Writing to this register will update the contents of the corresponding bit in
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* the Port Data Output Register (PDOR) as follows:
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*
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* Values:
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* - 0 - Corresponding bit in PDORn does not change.
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* - 1 - Corresponding bit in PDORn is cleared to logic 0.
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*/
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//@{
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#define BP_GPIO_PCOR_PTCO (0U) //!< Bit position for GPIO_PCOR_PTCO.
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#define BM_GPIO_PCOR_PTCO (0xFFFFFFFFU) //!< Bit mask for GPIO_PCOR_PTCO.
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#define BS_GPIO_PCOR_PTCO (32U) //!< Bit field size in bits for GPIO_PCOR_PTCO.
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//! @brief Format value for bitfield GPIO_PCOR_PTCO.
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#define BF_GPIO_PCOR_PTCO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PCOR_PTCO), uint32_t) & BM_GPIO_PCOR_PTCO)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the PTCO field to a new value.
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#define BW_GPIO_PCOR_PTCO(x, v) (HW_GPIO_PCOR_WR(x, v))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_GPIO_PTOR - Port Toggle Output Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_GPIO_PTOR - Port Toggle Output Register (WORZ)
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*
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* Reset value: 0x00000000U
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*/
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typedef union _hw_gpio_ptor
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{
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uint32_t U;
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struct _hw_gpio_ptor_bitfields
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{
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uint32_t PTTO : 32; //!< [31:0] Port Toggle Output
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} B;
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} hw_gpio_ptor_t;
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#endif
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/*!
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* @name Constants and macros for entire GPIO_PTOR register
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*/
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//@{
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#define HW_GPIO_PTOR_ADDR(x) (REGS_GPIO_BASE(x) + 0xCU)
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#ifndef __LANGUAGE_ASM__
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#define HW_GPIO_PTOR(x) (*(__O hw_gpio_ptor_t *) HW_GPIO_PTOR_ADDR(x))
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#define HW_GPIO_PTOR_RD(x) (HW_GPIO_PTOR(x).U)
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#define HW_GPIO_PTOR_WR(x, v) (HW_GPIO_PTOR(x).U = (v))
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#endif
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//@}
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/*
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* Constants & macros for individual GPIO_PTOR bitfields
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*/
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/*!
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* @name Register GPIO_PTOR, field PTTO[31:0] (WORZ)
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*
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* Writing to this register will update the contents of the corresponding bit in
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* the PDOR as follows:
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*
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* Values:
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* - 0 - Corresponding bit in PDORn does not change.
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* - 1 - Corresponding bit in PDORn is set to the inverse of its existing logic
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* state.
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*/
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//@{
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#define BP_GPIO_PTOR_PTTO (0U) //!< Bit position for GPIO_PTOR_PTTO.
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#define BM_GPIO_PTOR_PTTO (0xFFFFFFFFU) //!< Bit mask for GPIO_PTOR_PTTO.
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#define BS_GPIO_PTOR_PTTO (32U) //!< Bit field size in bits for GPIO_PTOR_PTTO.
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//! @brief Format value for bitfield GPIO_PTOR_PTTO.
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#define BF_GPIO_PTOR_PTTO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PTOR_PTTO), uint32_t) & BM_GPIO_PTOR_PTTO)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the PTTO field to a new value.
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#define BW_GPIO_PTOR_PTTO(x, v) (HW_GPIO_PTOR_WR(x, v))
|
||
|
|
#endif
|
||
|
|
//@}
|
||
|
|
|
||
|
|
//-------------------------------------------------------------------------------------------
|
||
|
|
// HW_GPIO_PDIR - Port Data Input Register
|
||
|
|
//-------------------------------------------------------------------------------------------
|
||
|
|
|
||
|
|
#ifndef __LANGUAGE_ASM__
|
||
|
|
/*!
|
||
|
|
* @brief HW_GPIO_PDIR - Port Data Input Register (RO)
|
||
|
|
*
|
||
|
|
* Reset value: 0x00000000U
|
||
|
|
*
|
||
|
|
* Do not modify pin configuration registers associated with pins not available
|
||
|
|
* in your selected package. All unbonded pins not available in your package will
|
||
|
|
* default to DISABLE state for lowest power consumption.
|
||
|
|
*/
|
||
|
|
typedef union _hw_gpio_pdir
|
||
|
|
{
|
||
|
|
uint32_t U;
|
||
|
|
struct _hw_gpio_pdir_bitfields
|
||
|
|
{
|
||
|
|
uint32_t PDI : 32; //!< [31:0] Port Data Input
|
||
|
|
} B;
|
||
|
|
} hw_gpio_pdir_t;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @name Constants and macros for entire GPIO_PDIR register
|
||
|
|
*/
|
||
|
|
//@{
|
||
|
|
#define HW_GPIO_PDIR_ADDR(x) (REGS_GPIO_BASE(x) + 0x10U)
|
||
|
|
|
||
|
|
#ifndef __LANGUAGE_ASM__
|
||
|
|
#define HW_GPIO_PDIR(x) (*(__I hw_gpio_pdir_t *) HW_GPIO_PDIR_ADDR(x))
|
||
|
|
#define HW_GPIO_PDIR_RD(x) (HW_GPIO_PDIR(x).U)
|
||
|
|
#endif
|
||
|
|
//@}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Constants & macros for individual GPIO_PDIR bitfields
|
||
|
|
*/
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @name Register GPIO_PDIR, field PDI[31:0] (RO)
|
||
|
|
*
|
||
|
|
* Reads 0 at the unimplemented pins for a particular device. Pins that are not
|
||
|
|
* configured for a digital function read 0. If the Port Control and Interrupt
|
||
|
|
* module is disabled, then the corresponding bit in PDIR does not update.
|
||
|
|
*
|
||
|
|
* Values:
|
||
|
|
* - 0 - Pin logic level is logic 0, or is not configured for use by digital
|
||
|
|
* function.
|
||
|
|
* - 1 - Pin logic level is logic 1.
|
||
|
|
*/
|
||
|
|
//@{
|
||
|
|
#define BP_GPIO_PDIR_PDI (0U) //!< Bit position for GPIO_PDIR_PDI.
|
||
|
|
#define BM_GPIO_PDIR_PDI (0xFFFFFFFFU) //!< Bit mask for GPIO_PDIR_PDI.
|
||
|
|
#define BS_GPIO_PDIR_PDI (32U) //!< Bit field size in bits for GPIO_PDIR_PDI.
|
||
|
|
|
||
|
|
#ifndef __LANGUAGE_ASM__
|
||
|
|
//! @brief Read current value of the GPIO_PDIR_PDI field.
|
||
|
|
#define BR_GPIO_PDIR_PDI(x) (HW_GPIO_PDIR(x).U)
|
||
|
|
#endif
|
||
|
|
//@}
|
||
|
|
|
||
|
|
//-------------------------------------------------------------------------------------------
|
||
|
|
// HW_GPIO_PDDR - Port Data Direction Register
|
||
|
|
//-------------------------------------------------------------------------------------------
|
||
|
|
|
||
|
|
#ifndef __LANGUAGE_ASM__
|
||
|
|
/*!
|
||
|
|
* @brief HW_GPIO_PDDR - Port Data Direction Register (RW)
|
||
|
|
*
|
||
|
|
* Reset value: 0x00000000U
|
||
|
|
*
|
||
|
|
* The PDDR configures the individual port pins for input or output.
|
||
|
|
*/
|
||
|
|
typedef union _hw_gpio_pddr
|
||
|
|
{
|
||
|
|
uint32_t U;
|
||
|
|
struct _hw_gpio_pddr_bitfields
|
||
|
|
{
|
||
|
|
uint32_t PDD : 32; //!< [31:0] Port Data Direction
|
||
|
|
} B;
|
||
|
|
} hw_gpio_pddr_t;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @name Constants and macros for entire GPIO_PDDR register
|
||
|
|
*/
|
||
|
|
//@{
|
||
|
|
#define HW_GPIO_PDDR_ADDR(x) (REGS_GPIO_BASE(x) + 0x14U)
|
||
|
|
|
||
|
|
#ifndef __LANGUAGE_ASM__
|
||
|
|
#define HW_GPIO_PDDR(x) (*(__IO hw_gpio_pddr_t *) HW_GPIO_PDDR_ADDR(x))
|
||
|
|
#define HW_GPIO_PDDR_RD(x) (HW_GPIO_PDDR(x).U)
|
||
|
|
#define HW_GPIO_PDDR_WR(x, v) (HW_GPIO_PDDR(x).U = (v))
|
||
|
|
#define HW_GPIO_PDDR_SET(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) | (v)))
|
||
|
|
#define HW_GPIO_PDDR_CLR(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) & ~(v)))
|
||
|
|
#define HW_GPIO_PDDR_TOG(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) ^ (v)))
|
||
|
|
#endif
|
||
|
|
//@}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Constants & macros for individual GPIO_PDDR bitfields
|
||
|
|
*/
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @name Register GPIO_PDDR, field PDD[31:0] (RW)
|
||
|
|
*
|
||
|
|
* Configures individual port pins for input or output.
|
||
|
|
*
|
||
|
|
* Values:
|
||
|
|
* - 0 - Pin is configured as general-purpose input, for the GPIO function.
|
||
|
|
* - 1 - Pin is configured as general-purpose output, for the GPIO function.
|
||
|
|
*/
|
||
|
|
//@{
|
||
|
|
#define BP_GPIO_PDDR_PDD (0U) //!< Bit position for GPIO_PDDR_PDD.
|
||
|
|
#define BM_GPIO_PDDR_PDD (0xFFFFFFFFU) //!< Bit mask for GPIO_PDDR_PDD.
|
||
|
|
#define BS_GPIO_PDDR_PDD (32U) //!< Bit field size in bits for GPIO_PDDR_PDD.
|
||
|
|
|
||
|
|
#ifndef __LANGUAGE_ASM__
|
||
|
|
//! @brief Read current value of the GPIO_PDDR_PDD field.
|
||
|
|
#define BR_GPIO_PDDR_PDD(x) (HW_GPIO_PDDR(x).U)
|
||
|
|
#endif
|
||
|
|
|
||
|
|
//! @brief Format value for bitfield GPIO_PDDR_PDD.
|
||
|
|
#define BF_GPIO_PDDR_PDD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PDDR_PDD), uint32_t) & BM_GPIO_PDDR_PDD)
|
||
|
|
|
||
|
|
#ifndef __LANGUAGE_ASM__
|
||
|
|
//! @brief Set the PDD field to a new value.
|
||
|
|
#define BW_GPIO_PDDR_PDD(x, v) (HW_GPIO_PDDR_WR(x, v))
|
||
|
|
#endif
|
||
|
|
//@}
|
||
|
|
|
||
|
|
//-------------------------------------------------------------------------------------------
|
||
|
|
// hw_gpio_t - module struct
|
||
|
|
//-------------------------------------------------------------------------------------------
|
||
|
|
/*!
|
||
|
|
* @brief All GPIO module registers.
|
||
|
|
*/
|
||
|
|
#ifndef __LANGUAGE_ASM__
|
||
|
|
#pragma pack(1)
|
||
|
|
typedef struct _hw_gpio
|
||
|
|
{
|
||
|
|
__IO hw_gpio_pdor_t PDOR; //!< [0x0] Port Data Output Register
|
||
|
|
__O hw_gpio_psor_t PSOR; //!< [0x4] Port Set Output Register
|
||
|
|
__O hw_gpio_pcor_t PCOR; //!< [0x8] Port Clear Output Register
|
||
|
|
__O hw_gpio_ptor_t PTOR; //!< [0xC] Port Toggle Output Register
|
||
|
|
__I hw_gpio_pdir_t PDIR; //!< [0x10] Port Data Input Register
|
||
|
|
__IO hw_gpio_pddr_t PDDR; //!< [0x14] Port Data Direction Register
|
||
|
|
} hw_gpio_t;
|
||
|
|
#pragma pack()
|
||
|
|
|
||
|
|
//! @brief Macro to access all GPIO registers.
|
||
|
|
//! @param x GPIO instance number.
|
||
|
|
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
||
|
|
//! use the '&' operator, like <code>&HW_GPIO(0)</code>.
|
||
|
|
#define HW_GPIO(x) (*(hw_gpio_t *) REGS_GPIO_BASE(x))
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif // __HW_GPIO_REGISTERS_H__
|
||
|
|
// v22/130726/0.9
|
||
|
|
// EOF
|