2022-09-06 12:48:16 +08:00
|
|
|
/*
|
2024-05-31 19:46:47 +08:00
|
|
|
* Copyright (c) 2021-2024 HPMicro
|
2022-09-06 12:48:16 +08:00
|
|
|
*
|
|
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
|
|
|
*
|
|
|
|
* Change Logs:
|
|
|
|
* Date Author Notes
|
2023-08-15 18:41:20 +08:00
|
|
|
* 2022-01-11 HPMicro First version
|
|
|
|
* 2022-07-28 HPMicro Fixed compiling warnings
|
|
|
|
* 2023-05-08 HPMicro Adapt RT-Thread V5.0.0
|
|
|
|
* 2023-08-15 HPMicro Enable pad loopback feature
|
2024-05-31 19:46:47 +08:00
|
|
|
* 2024-01-08 HPMicro Implemented pin_get
|
|
|
|
* 2024-04-17 HPMicro Refined pin irq implementation
|
|
|
|
* 2024-05-31 HPMicro Adapt later PIN driver framework
|
2024-08-12 16:48:39 +08:00
|
|
|
* 2024-07-03 HPMicro Determined the existence of GPIO via GPIO_DO_GPIOx macro
|
2022-09-06 12:48:16 +08:00
|
|
|
*/
|
|
|
|
|
|
|
|
#include <rtthread.h>
|
|
|
|
|
|
|
|
#ifdef BSP_USING_GPIO
|
|
|
|
#include <rthw.h>
|
|
|
|
#include <rtdevice.h>
|
|
|
|
#include "board.h"
|
|
|
|
#include "drv_gpio.h"
|
|
|
|
#include "hpm_gpio_drv.h"
|
|
|
|
#include "hpm_gpiom_drv.h"
|
|
|
|
#include "hpm_clock_drv.h"
|
2023-08-15 18:41:20 +08:00
|
|
|
#include "hpm_soc_feature.h"
|
2022-09-06 12:48:16 +08:00
|
|
|
|
2024-05-31 19:46:47 +08:00
|
|
|
|
2022-09-06 12:48:16 +08:00
|
|
|
typedef struct
|
|
|
|
{
|
|
|
|
uint32_t gpio_idx;
|
|
|
|
uint32_t irq_num;
|
2024-05-31 19:46:47 +08:00
|
|
|
struct rt_pin_irq_hdr *pin_irq_tbl;
|
2022-09-06 12:48:16 +08:00
|
|
|
} gpio_irq_map_t;
|
|
|
|
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOA
|
2024-05-31 19:46:47 +08:00
|
|
|
static struct rt_pin_irq_hdr hpm_gpio0_a_pin_hdr[32];
|
|
|
|
#endif
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOB
|
2024-05-31 19:46:47 +08:00
|
|
|
static struct rt_pin_irq_hdr hpm_gpio0_b_pin_hdr[32];
|
|
|
|
#endif
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOC
|
2024-05-31 19:46:47 +08:00
|
|
|
static struct rt_pin_irq_hdr hpm_gpio0_c_pin_hdr[32];
|
|
|
|
#endif
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOD
|
2024-05-31 19:46:47 +08:00
|
|
|
static struct rt_pin_irq_hdr hpm_gpio0_d_pin_hdr[32];
|
|
|
|
#endif
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOE
|
2024-05-31 19:46:47 +08:00
|
|
|
static struct rt_pin_irq_hdr hpm_gpio0_e_pin_hdr[32];
|
|
|
|
#endif
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOF
|
2024-05-31 19:46:47 +08:00
|
|
|
static struct rt_pin_irq_hdr hpm_gpio0_f_pin_hdr[32];
|
|
|
|
#endif
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOV
|
2024-05-31 19:46:47 +08:00
|
|
|
static struct rt_pin_irq_hdr hpm_gpio0_v_pin_hdr[32];
|
|
|
|
#endif
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOW
|
2024-05-31 19:46:47 +08:00
|
|
|
static struct rt_pin_irq_hdr hpm_gpio0_w_pin_hdr[32];
|
|
|
|
#endif
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOX
|
2024-05-31 19:46:47 +08:00
|
|
|
static struct rt_pin_irq_hdr hpm_gpio0_x_pin_hdr[32];
|
|
|
|
#endif
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOY
|
2024-05-31 19:46:47 +08:00
|
|
|
static struct rt_pin_irq_hdr hpm_gpio0_y_pin_hdr[32];
|
|
|
|
#endif
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOZ
|
2024-05-31 19:46:47 +08:00
|
|
|
static struct rt_pin_irq_hdr hpm_gpio0_z_pin_hdr[32];
|
|
|
|
#endif
|
|
|
|
|
2022-09-06 12:48:16 +08:00
|
|
|
static const gpio_irq_map_t hpm_gpio_irq_map[] = {
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOA
|
2024-05-31 19:46:47 +08:00
|
|
|
{ GPIO_IE_GPIOA, IRQn_GPIO0_A, hpm_gpio0_a_pin_hdr },
|
2022-09-06 12:48:16 +08:00
|
|
|
#endif
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOB
|
2024-05-31 19:46:47 +08:00
|
|
|
{ GPIO_IE_GPIOB, IRQn_GPIO0_B, hpm_gpio0_b_pin_hdr },
|
2022-09-06 12:48:16 +08:00
|
|
|
#endif
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOC
|
2024-05-31 19:46:47 +08:00
|
|
|
{ GPIO_IE_GPIOC, IRQn_GPIO0_C, hpm_gpio0_c_pin_hdr },
|
2022-09-06 12:48:16 +08:00
|
|
|
#endif
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOD
|
2024-05-31 19:46:47 +08:00
|
|
|
{ GPIO_IE_GPIOD, IRQn_GPIO0_D, hpm_gpio0_d_pin_hdr },
|
2022-09-06 12:48:16 +08:00
|
|
|
#endif
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOE
|
2024-05-31 19:46:47 +08:00
|
|
|
{ GPIO_IE_GPIOE, IRQn_GPIO0_E, hpm_gpio0_e_pin_hdr },
|
2022-09-06 12:48:16 +08:00
|
|
|
#endif
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOF
|
2024-05-31 19:46:47 +08:00
|
|
|
{ GPIO_IE_GPIOF, IRQn_GPIO0_F, hpm_gpio0_f_pin_hdr },
|
|
|
|
#endif
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOV
|
2024-05-31 19:46:47 +08:00
|
|
|
{ GPIO_IE_GPIOV, IRQn_GPIO0_V, hpm_gpio0_v_pin_hdr },
|
|
|
|
#endif
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOW
|
2024-05-31 19:46:47 +08:00
|
|
|
{ GPIO_IE_GPIOW, IRQn_GPIO0_W, hpm_gpio0_w_pin_hdr },
|
2022-09-06 12:48:16 +08:00
|
|
|
#endif
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOX
|
2024-05-31 19:46:47 +08:00
|
|
|
{ GPIO_IE_GPIOX, IRQn_GPIO0_X, hpm_gpio0_x_pin_hdr },
|
2022-09-06 12:48:16 +08:00
|
|
|
#endif
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOY
|
2024-05-31 19:46:47 +08:00
|
|
|
{ GPIO_IE_GPIOY, IRQn_GPIO0_Y, hpm_gpio0_y_pin_hdr },
|
2022-09-06 12:48:16 +08:00
|
|
|
#endif
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOZ
|
2024-05-31 19:46:47 +08:00
|
|
|
{ GPIO_IE_GPIOZ, IRQn_GPIO0_Z, hpm_gpio0_z_pin_hdr },
|
2022-09-06 12:48:16 +08:00
|
|
|
#endif
|
2024-05-31 19:46:47 +08:00
|
|
|
};
|
2022-09-06 12:48:16 +08:00
|
|
|
|
2024-05-31 19:46:47 +08:00
|
|
|
static struct rt_pin_irq_hdr *lookup_pin_irq_hdr_tbl(rt_base_t pin)
|
|
|
|
{
|
|
|
|
struct rt_pin_irq_hdr *pin_irq_hdr_tbl = RT_NULL;
|
|
|
|
uint32_t gpio_idx = pin >> 5;
|
2022-09-06 12:48:16 +08:00
|
|
|
|
2024-05-31 19:46:47 +08:00
|
|
|
for (uint32_t i = 0; i < ARRAY_SIZE(hpm_gpio_irq_map); i++)
|
|
|
|
{
|
|
|
|
if (hpm_gpio_irq_map[i].gpio_idx == gpio_idx)
|
|
|
|
{
|
|
|
|
pin_irq_hdr_tbl = hpm_gpio_irq_map[i].pin_irq_tbl;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return pin_irq_hdr_tbl;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int hpm_get_gpio_irq_num(uint32_t gpio_idx)
|
2022-09-06 12:48:16 +08:00
|
|
|
{
|
|
|
|
int irq_num = -1;
|
|
|
|
|
2024-05-31 19:46:47 +08:00
|
|
|
for (uint32_t i = 0; i < ARRAY_SIZE(hpm_gpio_irq_map); i++)
|
2022-09-06 12:48:16 +08:00
|
|
|
{
|
|
|
|
if (hpm_gpio_irq_map[i].gpio_idx == gpio_idx)
|
|
|
|
{
|
|
|
|
irq_num = hpm_gpio_irq_map[i].irq_num;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return irq_num;
|
|
|
|
}
|
|
|
|
|
2024-05-31 19:46:47 +08:00
|
|
|
static void hpm_gpio_isr(uint32_t gpio_idx, GPIO_Type *base)
|
2022-09-06 12:48:16 +08:00
|
|
|
{
|
2024-05-31 19:46:47 +08:00
|
|
|
/* Lookup the Pin IRQ Header Table */
|
|
|
|
struct rt_pin_irq_hdr *pin_irq_hdr = RT_NULL;
|
|
|
|
for (uint32_t i = 0; i < ARRAY_SIZE(hpm_gpio_irq_map); i++)
|
|
|
|
{
|
|
|
|
if (hpm_gpio_irq_map[i].gpio_idx == gpio_idx)
|
|
|
|
{
|
|
|
|
pin_irq_hdr = hpm_gpio_irq_map[i].pin_irq_tbl;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for(uint32_t pin_idx = 0; pin_idx < 32; pin_idx++)
|
2022-09-06 12:48:16 +08:00
|
|
|
{
|
2024-05-31 19:46:47 +08:00
|
|
|
if (gpio_check_pin_interrupt_flag(base, gpio_idx, pin_idx))
|
2022-09-06 12:48:16 +08:00
|
|
|
{
|
2024-05-31 19:46:47 +08:00
|
|
|
gpio_clear_pin_interrupt_flag(base, gpio_idx, pin_idx);
|
|
|
|
|
|
|
|
if (pin_irq_hdr[pin_idx].hdr != RT_NULL)
|
2022-09-06 12:48:16 +08:00
|
|
|
{
|
2024-05-31 19:46:47 +08:00
|
|
|
pin_irq_hdr[pin_idx].hdr(pin_irq_hdr[pin_idx].args);
|
2022-09-06 12:48:16 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOA
|
2022-09-06 12:48:16 +08:00
|
|
|
void gpioa_isr(void)
|
|
|
|
{
|
|
|
|
hpm_gpio_isr(GPIO_IF_GPIOA, HPM_GPIO0);
|
|
|
|
}
|
|
|
|
SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_A, gpioa_isr)
|
|
|
|
#endif
|
|
|
|
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOB
|
2022-09-06 12:48:16 +08:00
|
|
|
void gpiob_isr(void)
|
|
|
|
{
|
|
|
|
hpm_gpio_isr(GPIO_IF_GPIOB, HPM_GPIO0);
|
|
|
|
}
|
|
|
|
SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_B, gpiob_isr)
|
|
|
|
#endif
|
|
|
|
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOC
|
2022-09-06 12:48:16 +08:00
|
|
|
void gpioc_isr(void)
|
|
|
|
{
|
|
|
|
hpm_gpio_isr(GPIO_IF_GPIOC, HPM_GPIO0);
|
|
|
|
}
|
|
|
|
SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_C, gpioc_isr)
|
|
|
|
#endif
|
|
|
|
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOD
|
2022-09-06 12:48:16 +08:00
|
|
|
void gpiod_isr(void)
|
|
|
|
{
|
|
|
|
hpm_gpio_isr(GPIO_IF_GPIOD, HPM_GPIO0);
|
|
|
|
}
|
|
|
|
SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_D, gpiod_isr)
|
|
|
|
#endif
|
|
|
|
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOE
|
2022-09-06 12:48:16 +08:00
|
|
|
void gpioe_isr(void)
|
|
|
|
{
|
|
|
|
hpm_gpio_isr(GPIO_IF_GPIOE, HPM_GPIO0);
|
|
|
|
}
|
|
|
|
SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_E, gpioe_isr)
|
|
|
|
#endif
|
|
|
|
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOF
|
2022-09-06 12:48:16 +08:00
|
|
|
void gpiof_isr(void)
|
|
|
|
{
|
|
|
|
hpm_gpio_isr(GPIO_IF_GPIOF, HPM_GPIO0);
|
|
|
|
}
|
|
|
|
SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_F, gpiof_isr)
|
|
|
|
#endif
|
|
|
|
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOV
|
|
|
|
void gpiov_isr(void)
|
2024-05-31 19:46:47 +08:00
|
|
|
{
|
|
|
|
hpm_gpio_isr(GPIO_IF_GPIOV, HPM_GPIO0);
|
|
|
|
}
|
|
|
|
SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_V, gpiox_isr)
|
|
|
|
#endif
|
|
|
|
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOW
|
|
|
|
void gpiow_isr(void)
|
2024-05-31 19:46:47 +08:00
|
|
|
{
|
|
|
|
hpm_gpio_isr(GPIO_IF_GPIOW, HPM_GPIO0);
|
|
|
|
}
|
|
|
|
SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_W, gpiox_isr)
|
|
|
|
#endif
|
|
|
|
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOX
|
2022-09-06 12:48:16 +08:00
|
|
|
void gpiox_isr(void)
|
|
|
|
{
|
|
|
|
hpm_gpio_isr(GPIO_IF_GPIOX, HPM_GPIO0);
|
|
|
|
}
|
|
|
|
SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_X, gpiox_isr)
|
|
|
|
#endif
|
|
|
|
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOY
|
2022-09-06 12:48:16 +08:00
|
|
|
void gpioy_isr(void)
|
|
|
|
{
|
|
|
|
hpm_gpio_isr(GPIO_IF_GPIOY, HPM_GPIO0);
|
|
|
|
}
|
|
|
|
SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_Y, gpioy_isr)
|
|
|
|
#endif
|
|
|
|
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DO_GPIOZ
|
2022-09-06 12:48:16 +08:00
|
|
|
void gpioz_isr(void)
|
|
|
|
{
|
|
|
|
hpm_gpio_isr(GPIO_IF_GPIOZ, HPM_GPIO0);
|
|
|
|
}
|
|
|
|
SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_Z, gpioz_isr)
|
|
|
|
#endif
|
|
|
|
|
2024-05-31 19:46:47 +08:00
|
|
|
/**
|
|
|
|
* @brief Get Pin index from name
|
|
|
|
*
|
|
|
|
* Name rule is : <GPIO NAME><Index>
|
|
|
|
* for example: PA00, PZ03
|
|
|
|
*
|
|
|
|
**/
|
|
|
|
static rt_base_t hpm_pin_get(const char *name)
|
|
|
|
{
|
|
|
|
if (!( (rt_strlen(name) == 4) &&
|
|
|
|
(name[0] == 'P') &&
|
|
|
|
((('A' <= name[1]) && (name[1] <= 'F')) || (('V' <= name[1]) && (name[1] <= 'Z'))) &&
|
|
|
|
(('0' <= name[2]) && (name[2] <= '9')) &&
|
|
|
|
(('0' <= name[3]) && (name[3] <= '9'))
|
|
|
|
))
|
|
|
|
{
|
|
|
|
return -RT_EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t gpio_idx = (name[1] <= 'F') ? (name[1] - 'A') : (11 + name[1] - 'V');
|
|
|
|
uint32_t pin_idx = (uint32_t)(name[2] - '0') * 10 + (name[3] - '0');
|
|
|
|
return (gpio_idx * 32 + pin_idx);
|
|
|
|
}
|
2022-09-06 12:48:16 +08:00
|
|
|
|
2023-05-09 11:35:27 +08:00
|
|
|
static void hpm_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
|
2022-09-06 12:48:16 +08:00
|
|
|
{
|
|
|
|
/* TODO: Check the validity of the pin value */
|
|
|
|
uint32_t gpio_idx = pin >> 5;
|
|
|
|
uint32_t pin_idx = pin & 0x1FU;
|
|
|
|
|
|
|
|
gpiom_set_pin_controller(HPM_GPIOM, gpio_idx, pin_idx, gpiom_soc_gpio0);
|
|
|
|
|
|
|
|
HPM_IOC->PAD[pin].FUNC_CTL = 0;
|
|
|
|
|
|
|
|
switch (gpio_idx)
|
|
|
|
{
|
|
|
|
case GPIO_DI_GPIOY :
|
|
|
|
HPM_PIOC->PAD[pin].FUNC_CTL = 3;
|
|
|
|
break;
|
2024-08-12 16:48:39 +08:00
|
|
|
#ifdef GPIO_DI_GPIOZ
|
2022-09-06 12:48:16 +08:00
|
|
|
case GPIO_DI_GPIOZ :
|
2024-05-31 19:46:47 +08:00
|
|
|
#ifdef HPM_BIOC
|
2022-09-06 12:48:16 +08:00
|
|
|
HPM_BIOC->PAD[pin].FUNC_CTL = 3;
|
2024-05-31 19:46:47 +08:00
|
|
|
#endif
|
2022-09-06 12:48:16 +08:00
|
|
|
break;
|
2024-08-12 16:48:39 +08:00
|
|
|
#endif
|
2022-09-06 12:48:16 +08:00
|
|
|
default :
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (mode)
|
|
|
|
{
|
|
|
|
case PIN_MODE_OUTPUT:
|
|
|
|
gpio_set_pin_output(HPM_GPIO0, gpio_idx, pin_idx);
|
|
|
|
HPM_IOC->PAD[pin].PAD_CTL &= ~(IOC_PAD_PAD_CTL_PS_MASK | IOC_PAD_PAD_CTL_PE_MASK | IOC_PAD_PAD_CTL_OD_MASK);
|
|
|
|
break;
|
|
|
|
case PIN_MODE_INPUT:
|
|
|
|
gpio_set_pin_input(HPM_GPIO0, gpio_idx, pin_idx);
|
|
|
|
HPM_IOC->PAD[pin].PAD_CTL &= ~(IOC_PAD_PAD_CTL_PS_MASK | IOC_PAD_PAD_CTL_PE_MASK);
|
|
|
|
break;
|
|
|
|
case PIN_MODE_INPUT_PULLDOWN:
|
|
|
|
gpio_set_pin_input(HPM_GPIO0, gpio_idx, pin_idx);
|
|
|
|
HPM_IOC->PAD[pin].PAD_CTL = (HPM_IOC->PAD[pin].PAD_CTL & ~IOC_PAD_PAD_CTL_PS_MASK) | IOC_PAD_PAD_CTL_PE_SET(1);
|
|
|
|
break;
|
|
|
|
case PIN_MODE_INPUT_PULLUP:
|
|
|
|
gpio_set_pin_input(HPM_GPIO0, gpio_idx, pin_idx);
|
|
|
|
HPM_IOC->PAD[pin].PAD_CTL |= IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
|
|
|
|
break;
|
|
|
|
case PIN_MODE_OUTPUT_OD:
|
|
|
|
gpio_set_pin_output(HPM_GPIO0, gpio_idx, pin_idx);
|
|
|
|
HPM_IOC->PAD[pin].PAD_CTL = (HPM_IOC->PAD[pin].PAD_CTL & ~(IOC_PAD_PAD_CTL_PS_MASK | IOC_PAD_PAD_CTL_PE_MASK)) | IOC_PAD_PAD_CTL_OD_SET(1);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
/* Invalid mode */
|
|
|
|
break;
|
|
|
|
}
|
2023-08-15 18:41:20 +08:00
|
|
|
HPM_IOC->PAD[pin].FUNC_CTL = IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
2022-09-06 12:48:16 +08:00
|
|
|
}
|
|
|
|
|
2024-03-24 02:50:31 +08:00
|
|
|
static rt_ssize_t hpm_pin_read(rt_device_t dev, rt_base_t pin)
|
2022-09-06 12:48:16 +08:00
|
|
|
{
|
|
|
|
/* TODO: Check the validity of the pin value */
|
|
|
|
uint32_t gpio_idx = pin >> 5;
|
|
|
|
uint32_t pin_idx = pin & 0x1FU;
|
|
|
|
|
2024-03-24 02:50:31 +08:00
|
|
|
return (rt_ssize_t) gpio_read_pin(HPM_GPIO0, gpio_idx, pin_idx);
|
2022-09-06 12:48:16 +08:00
|
|
|
}
|
|
|
|
|
2023-05-09 11:35:27 +08:00
|
|
|
static void hpm_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
|
2022-09-06 12:48:16 +08:00
|
|
|
{
|
|
|
|
/* TODO: Check the validity of the pin value */
|
|
|
|
uint32_t gpio_idx = pin >> 5;
|
|
|
|
uint32_t pin_idx = pin & 0x1FU;
|
|
|
|
|
|
|
|
gpio_write_pin(HPM_GPIO0, gpio_idx, pin_idx, value);
|
|
|
|
}
|
|
|
|
|
2023-08-15 18:41:20 +08:00
|
|
|
static rt_err_t hpm_pin_attach_irq(struct rt_device *device,
|
|
|
|
rt_base_t pin,
|
|
|
|
rt_uint8_t mode,
|
|
|
|
void (*hdr)(void *args),
|
|
|
|
void *args)
|
2022-09-06 12:48:16 +08:00
|
|
|
{
|
2024-05-31 19:46:47 +08:00
|
|
|
struct rt_pin_irq_hdr *pin_irq_hdr_tbl = lookup_pin_irq_hdr_tbl(pin);
|
|
|
|
if (pin_irq_hdr_tbl == RT_NULL)
|
|
|
|
{
|
|
|
|
return -RT_EINVAL;
|
|
|
|
}
|
2022-09-06 12:48:16 +08:00
|
|
|
|
2024-05-31 19:46:47 +08:00
|
|
|
rt_base_t level = rt_hw_interrupt_disable();
|
|
|
|
uint32_t pin_idx = pin & 0x1FUL;
|
|
|
|
pin_irq_hdr_tbl[pin_idx].pin = pin;
|
|
|
|
pin_irq_hdr_tbl[pin_idx].hdr = hdr;
|
|
|
|
pin_irq_hdr_tbl[pin_idx].mode = mode;
|
|
|
|
pin_irq_hdr_tbl[pin_idx].args = args;
|
2022-09-06 12:48:16 +08:00
|
|
|
rt_hw_interrupt_enable(level);
|
|
|
|
|
|
|
|
return RT_EOK;
|
|
|
|
}
|
|
|
|
|
2023-05-09 11:35:27 +08:00
|
|
|
static rt_err_t hpm_pin_detach_irq(struct rt_device *device, rt_base_t pin)
|
2022-09-06 12:48:16 +08:00
|
|
|
{
|
2024-05-31 19:46:47 +08:00
|
|
|
struct rt_pin_irq_hdr *pin_irq_hdr_tbl = lookup_pin_irq_hdr_tbl(pin);
|
|
|
|
if (pin_irq_hdr_tbl == RT_NULL)
|
|
|
|
{
|
|
|
|
return -RT_EINVAL;
|
|
|
|
}
|
|
|
|
rt_base_t level = rt_hw_interrupt_disable();
|
|
|
|
uint32_t pin_idx = pin & 0x1FUL;
|
|
|
|
pin_irq_hdr_tbl[pin_idx].pin = -1;
|
|
|
|
pin_irq_hdr_tbl[pin_idx].hdr = RT_NULL;
|
|
|
|
pin_irq_hdr_tbl[pin_idx].mode = 0;
|
|
|
|
pin_irq_hdr_tbl[pin_idx].args = RT_NULL;
|
2022-09-06 12:48:16 +08:00
|
|
|
rt_hw_interrupt_enable(level);
|
|
|
|
|
|
|
|
return RT_EOK;
|
|
|
|
}
|
|
|
|
|
2023-05-09 11:35:27 +08:00
|
|
|
static rt_err_t hpm_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
|
2022-09-06 12:48:16 +08:00
|
|
|
{
|
|
|
|
/* TODO: Check the validity of the pin value */
|
|
|
|
uint32_t gpio_idx = pin >> 5;
|
|
|
|
uint32_t pin_idx = pin & 0x1FU;
|
|
|
|
|
2024-05-31 19:46:47 +08:00
|
|
|
struct rt_pin_irq_hdr *pin_irq_hdr_tbl = lookup_pin_irq_hdr_tbl(pin);
|
|
|
|
if (pin_irq_hdr_tbl == RT_NULL)
|
|
|
|
{
|
|
|
|
return -RT_EINVAL;
|
|
|
|
}
|
|
|
|
|
2022-09-06 12:48:16 +08:00
|
|
|
gpio_interrupt_trigger_t trigger;
|
|
|
|
if (enabled == PIN_IRQ_ENABLE)
|
|
|
|
{
|
2024-05-31 19:46:47 +08:00
|
|
|
switch(pin_irq_hdr_tbl[pin_idx].mode)
|
2022-09-06 12:48:16 +08:00
|
|
|
{
|
|
|
|
case PIN_IRQ_MODE_RISING:
|
|
|
|
trigger = gpio_interrupt_trigger_edge_rising;
|
|
|
|
break;
|
|
|
|
case PIN_IRQ_MODE_FALLING:
|
|
|
|
trigger = gpio_interrupt_trigger_edge_falling;
|
|
|
|
break;
|
|
|
|
case PIN_IRQ_MODE_HIGH_LEVEL:
|
|
|
|
trigger = gpio_interrupt_trigger_level_high;
|
|
|
|
break;
|
|
|
|
case PIN_IRQ_MODE_LOW_LEVEL:
|
|
|
|
trigger = gpio_interrupt_trigger_level_low;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
trigger = gpio_interrupt_trigger_edge_rising;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
gpio_config_pin_interrupt(HPM_GPIO0, gpio_idx, pin_idx, trigger);
|
2024-05-31 19:46:47 +08:00
|
|
|
uint32_t irq_num = hpm_get_gpio_irq_num(gpio_idx);
|
2022-09-06 12:48:16 +08:00
|
|
|
gpio_enable_pin_interrupt(HPM_GPIO0, gpio_idx, pin_idx);
|
|
|
|
intc_m_enable_irq_with_priority(irq_num, 1);
|
|
|
|
}
|
|
|
|
else if (enabled == PIN_IRQ_DISABLE)
|
|
|
|
{
|
|
|
|
gpio_disable_pin_interrupt(HPM_GPIO0, gpio_idx, pin_idx);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2024-05-31 19:46:47 +08:00
|
|
|
return -RT_EINVAL;
|
2022-09-06 12:48:16 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return RT_EOK;
|
|
|
|
}
|
|
|
|
|
2024-05-31 19:46:47 +08:00
|
|
|
const static struct rt_pin_ops hpm_pin_ops = {
|
|
|
|
.pin_mode = hpm_pin_mode,
|
|
|
|
.pin_write = hpm_pin_write,
|
|
|
|
.pin_read = hpm_pin_read,
|
|
|
|
.pin_attach_irq = hpm_pin_attach_irq,
|
|
|
|
.pin_detach_irq = hpm_pin_detach_irq,
|
|
|
|
.pin_irq_enable = hpm_pin_irq_enable,
|
|
|
|
.pin_get = hpm_pin_get,
|
2024-03-24 09:04:19 +08:00
|
|
|
};
|
2022-09-06 12:48:16 +08:00
|
|
|
|
|
|
|
int rt_hw_pin_init(void)
|
|
|
|
{
|
|
|
|
int ret = RT_EOK;
|
|
|
|
|
|
|
|
ret = rt_device_pin_register("pin", &hpm_pin_ops, RT_NULL);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
INIT_BOARD_EXPORT(rt_hw_pin_init);
|
|
|
|
|
|
|
|
#endif /* BSP_USING_GPIO */
|