2017-08-22 15:52:57 +08:00
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/*!
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2021-06-09 16:24:20 +08:00
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\file gd32f4xx_pmu.h
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\brief definitions for the PMU
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\version 2016-08-15, V1.0.0, firmware for GD32F4xx
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\version 2018-12-12, V2.0.0, firmware for GD32F4xx
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\version 2020-09-30, V2.1.0, firmware for GD32F4xx
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2017-08-22 15:52:57 +08:00
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*/
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/*
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2021-06-09 16:24:20 +08:00
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Copyright (c) 2020, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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2017-08-22 15:52:57 +08:00
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*/
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2021-06-09 16:24:20 +08:00
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2017-08-22 15:52:57 +08:00
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#ifndef GD32F4XX_PMU_H
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#define GD32F4XX_PMU_H
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#include "gd32f4xx.h"
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/* PMU definitions */
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#define PMU PMU_BASE /*!< PMU base address */
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/* registers definitions */
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#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */
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#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */
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/* bits definitions */
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/* PMU_CTL */
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#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */
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#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */
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#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */
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#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */
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#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */
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#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */
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#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */
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#define PMU_CTL_LDLP BIT(10) /*!< low-driver mode when use low power LDO */
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#define PMU_CTL_LDNP BIT(11) /*!< low-driver mode when use normal power LDO */
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#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */
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#define PMU_CTL_HDEN BIT(16) /*!< high-driver mode enable */
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#define PMU_CTL_HDS BIT(17) /*!< high-driver mode switch */
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#define PMU_CTL_LDEN BITS(18,19) /*!< low-driver mode enable in deep-sleep mode */
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/* PMU_CS */
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#define PMU_CS_WUF BIT(0) /*!< wakeup flag */
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#define PMU_CS_STBF BIT(1) /*!< standby flag */
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#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */
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#define PMU_CS_BLDORF BIT(3) /*!< backup SRAM LDO ready flag */
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#define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */
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#define PMU_CS_BLDOON BIT(9) /*!< backup SRAM LDO on */
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#define PMU_CS_LDOVSRF BIT(14) /*!< LDO voltage select ready flag */
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#define PMU_CS_HDRF BIT(16) /*!< high-driver ready flag */
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#define PMU_CS_HDSRF BIT(17) /*!< high-driver switch ready flag */
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#define PMU_CS_LDRF BITS(18,19) /*!< Low-driver mode ready flag */
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/* constants definitions */
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/* PMU low voltage detector threshold definitions */
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#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5))
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#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */
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#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */
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#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */
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#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */
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#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */
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#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */
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#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */
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#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */
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/* PMU LDO output voltage select definitions */
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#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14))
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#define PMU_LDOVS_LOW CTL_LDOVS(1) /*!< LDO output voltage low mode */
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#define PMU_LDOVS_MID CTL_LDOVS(2) /*!< LDO output voltage mid mode */
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#define PMU_LDOVS_HIGH CTL_LDOVS(3) /*!< LDO output voltage high mode */
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/* PMU low-driver mode enable in deep-sleep mode */
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#define CTL_LDEN(regval) (BITS(18,19)&((uint32_t)(regval)<<18))
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#define PMU_LOWDRIVER_DISABLE CTL_LDEN(0) /*!< low-driver mode disable in deep-sleep mode */
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#define PMU_LOWDRIVER_ENABLE CTL_LDEN(3) /*!< low-driver mode enable in deep-sleep mode */
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/* PMU high-driver mode switch */
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#define CTL_HDS(regval) (BIT(17)&((uint32_t)(regval)<<17))
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#define PMU_HIGHDR_SWITCH_NONE CTL_HDS(0) /*!< no high-driver mode switch */
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#define PMU_HIGHDR_SWITCH_EN CTL_HDS(1) /*!< high-driver mode switch */
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/* PMU low-driver mode when use low power LDO */
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#define CTL_LDLP(regval) (BIT(10)&((uint32_t)(regval)<<10))
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#define PMU_NORMALDR_LOWPWR CTL_LDLP(0) /*!< normal driver when use low power LDO */
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#define PMU_LOWDR_LOWPWR CTL_LDLP(1) /*!< low-driver mode enabled when LDEN is 11 and use low power LDO */
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/* PMU low-driver mode when use normal power LDO */
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#define CTL_LDNP(regval) (BIT(11)&((uint32_t)(regval)<<11))
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#define PMU_NORMALDR_NORMALPWR CTL_LDNP(0) /*!< normal driver when use normal power LDO */
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#define PMU_LOWDR_NORMALPWR CTL_LDNP(1) /*!< low-driver mode enabled when LDEN is 11 and use normal power LDO */
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/* PMU low power mode ready flag definitions */
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#define CS_LDRF(regval) (BITS(18,19)&((uint32_t)(regval)<<18))
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#define PMU_LDRF_NORMAL CS_LDRF(0) /*!< normal driver in deep-sleep mode */
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#define PMU_LDRF_LOWDRIVER CS_LDRF(3) /*!< low-driver mode in deep-sleep mode */
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/* PMU backup SRAM LDO on or off */
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#define CS_BLDOON(regval) (BIT(9)&((uint32_t)(regval)<<9))
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#define PMU_BLDOON_OFF CS_BLDOON(0) /*!< backup SRAM LDO off */
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#define PMU_BLDOON_ON CS_BLDOON(1) /*!< the backup SRAM LDO on */
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/* PMU flag definitions */
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#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */
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#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */
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#define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */
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#define PMU_FLAG_BLDORF PMU_CS_BLDORF /*!< backup SRAM LDO ready flag */
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#define PMU_FLAG_LDOVSRF PMU_CS_LDOVSRF /*!< LDO voltage select ready flag */
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#define PMU_FLAG_HDRF PMU_CS_HDRF /*!< high-driver ready flag */
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#define PMU_FLAG_HDSRF PMU_CS_HDSRF /*!< high-driver switch ready flag */
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#define PMU_FLAG_LDRF PMU_CS_LDRF /*!< low-driver mode ready flag */
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/* PMU ldo definitions */
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#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */
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#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */
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/* PMU flag reset definitions */
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#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */
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#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */
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/* PMU command constants definitions */
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#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */
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#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */
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/* function declarations */
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/* reset PMU register */
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void pmu_deinit(void);
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/* select low voltage detector threshold */
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void pmu_lvd_select(uint32_t lvdt_n);
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/* LDO output voltage select */
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void pmu_ldo_output_select(uint32_t ldo_output);
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/* PMU lvd disable */
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void pmu_lvd_disable(void);
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/* functions of low-driver mode and high-driver mode in deep-sleep mode */
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/* high-driver mode switch */
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void pmu_highdriver_switch_select(uint32_t highdr_switch);
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/* high-driver mode enable */
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void pmu_highdriver_mode_enable(void);
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/* high-driver mode disable */
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void pmu_highdriver_mode_disable(void);
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/* low-driver mode enable in deep-sleep mode */
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void pmu_low_driver_mode_enable(uint32_t lowdr_mode);
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/* in deep-sleep mode, low-driver mode when use low power LDO */
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void pmu_lowdriver_lowpower_config(uint32_t mode);
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/* in deep-sleep mode, low-driver mode when use normal power LDO */
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void pmu_lowdriver_normalpower_config(uint32_t mode);
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/* set PMU mode */
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/* PMU work at sleep mode */
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void pmu_to_sleepmode(uint8_t sleepmodecmd);
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/* PMU work at deepsleep mode */
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void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd);
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/* PMU work at standby mode */
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void pmu_to_standbymode(uint8_t standbymodecmd);
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/* PMU wakeup pin enable */
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void pmu_wakeup_pin_enable(void);
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/* PMU wakeup pin disable */
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void pmu_wakeup_pin_disable(void);
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/* backup related functions */
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/* backup SRAM LDO on */
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void pmu_backup_ldo_config(uint32_t bkp_ldo);
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/* backup domain write enable */
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void pmu_backup_write_enable(void);
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/* backup domain write disable */
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void pmu_backup_write_disable(void);
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/* flag functions */
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/* reset flag bit */
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void pmu_flag_reset(uint32_t flag_reset);
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/* get flag status */
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FlagStatus pmu_flag_get(uint32_t pmu_flag);
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#endif /* GD32F4XX_PMU_H */
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