2017-08-22 15:52:57 +08:00
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/*!
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2021-06-09 16:24:20 +08:00
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\file gd32f4xx_can.h
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\brief definitions for the CAN
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\version 2016-08-15, V1.0.0, firmware for GD32F4xx
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\version 2018-12-12, V2.0.0, firmware for GD32F4xx
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\version 2019-11-27, V2.0.1, firmware for GD32F4xx
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\version 2020-09-30, V2.1.0, firmware for GD32F4xx
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2017-08-22 15:52:57 +08:00
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*/
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/*
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2021-06-09 16:24:20 +08:00
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Copyright (c) 2020, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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2017-08-22 15:52:57 +08:00
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*/
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#ifndef GD32F4XX_CAN_H
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#define GD32F4XX_CAN_H
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#include "gd32f4xx.h"
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/* CAN definitions */
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#define CAN0 CAN_BASE /*!< CAN0 base address */
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#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */
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/* registers definitions */
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#define CAN_CTL(canx) REG32((canx) + 0x00U) /*!< CAN control register */
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#define CAN_STAT(canx) REG32((canx) + 0x04U) /*!< CAN status register */
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#define CAN_TSTAT(canx) REG32((canx) + 0x08U) /*!< CAN transmit status register*/
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#define CAN_RFIFO0(canx) REG32((canx) + 0x0CU) /*!< CAN receive FIFO0 register */
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#define CAN_RFIFO1(canx) REG32((canx) + 0x10U) /*!< CAN receive FIFO1 register */
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#define CAN_INTEN(canx) REG32((canx) + 0x14U) /*!< CAN interrupt enable register */
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#define CAN_ERR(canx) REG32((canx) + 0x18U) /*!< CAN error register */
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#define CAN_BT(canx) REG32((canx) + 0x1CU) /*!< CAN bit timing register */
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#define CAN_TMI0(canx) REG32((canx) + 0x180U) /*!< CAN transmit mailbox0 identifier register */
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#define CAN_TMP0(canx) REG32((canx) + 0x184U) /*!< CAN transmit mailbox0 property register */
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#define CAN_TMDATA00(canx) REG32((canx) + 0x188U) /*!< CAN transmit mailbox0 data0 register */
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#define CAN_TMDATA10(canx) REG32((canx) + 0x18CU) /*!< CAN transmit mailbox0 data1 register */
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#define CAN_TMI1(canx) REG32((canx) + 0x190U) /*!< CAN transmit mailbox1 identifier register */
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#define CAN_TMP1(canx) REG32((canx) + 0x194U) /*!< CAN transmit mailbox1 property register */
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#define CAN_TMDATA01(canx) REG32((canx) + 0x198U) /*!< CAN transmit mailbox1 data0 register */
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#define CAN_TMDATA11(canx) REG32((canx) + 0x19CU) /*!< CAN transmit mailbox1 data1 register */
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#define CAN_TMI2(canx) REG32((canx) + 0x1A0U) /*!< CAN transmit mailbox2 identifier register */
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#define CAN_TMP2(canx) REG32((canx) + 0x1A4U) /*!< CAN transmit mailbox2 property register */
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#define CAN_TMDATA02(canx) REG32((canx) + 0x1A8U) /*!< CAN transmit mailbox2 data0 register */
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#define CAN_TMDATA12(canx) REG32((canx) + 0x1ACU) /*!< CAN transmit mailbox2 data1 register */
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#define CAN_RFIFOMI0(canx) REG32((canx) + 0x1B0U) /*!< CAN receive FIFO0 mailbox identifier register */
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#define CAN_RFIFOMP0(canx) REG32((canx) + 0x1B4U) /*!< CAN receive FIFO0 mailbox property register */
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#define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x1B8U) /*!< CAN receive FIFO0 mailbox data0 register */
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#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x1BCU) /*!< CAN receive FIFO0 mailbox data1 register */
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2017-08-22 15:52:57 +08:00
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#define CAN_RFIFOMI1(canx) REG32((canx) + 0x1C0U) /*!< CAN receive FIFO1 mailbox identifier register */
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#define CAN_RFIFOMP1(canx) REG32((canx) + 0x1C4U) /*!< CAN receive FIFO1 mailbox property register */
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#define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x1C8U) /*!< CAN receive FIFO1 mailbox data0 register */
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#define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x1CCU) /*!< CAN receive FIFO1 mailbox data1 register */
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#define CAN_FCTL(canx) REG32((canx) + 0x200U) /*!< CAN filter control register */
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#define CAN_FMCFG(canx) REG32((canx) + 0x204U) /*!< CAN filter mode register */
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#define CAN_FSCFG(canx) REG32((canx) + 0x20CU) /*!< CAN filter scale register */
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#define CAN_FAFIFO(canx) REG32((canx) + 0x214U) /*!< CAN filter associated FIFO register */
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#define CAN_FW(canx) REG32((canx) + 0x21CU) /*!< CAN filter working register */
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#define CAN_F0DATA0(canx) REG32((canx) + 0x240U) /*!< CAN filter 0 data 0 register */
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#define CAN_F1DATA0(canx) REG32((canx) + 0x248U) /*!< CAN filter 1 data 0 register */
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#define CAN_F2DATA0(canx) REG32((canx) + 0x250U) /*!< CAN filter 2 data 0 register */
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#define CAN_F3DATA0(canx) REG32((canx) + 0x258U) /*!< CAN filter 3 data 0 register */
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#define CAN_F4DATA0(canx) REG32((canx) + 0x260U) /*!< CAN filter 4 data 0 register */
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#define CAN_F5DATA0(canx) REG32((canx) + 0x268U) /*!< CAN filter 5 data 0 register */
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#define CAN_F6DATA0(canx) REG32((canx) + 0x270U) /*!< CAN filter 6 data 0 register */
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#define CAN_F7DATA0(canx) REG32((canx) + 0x278U) /*!< CAN filter 7 data 0 register */
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#define CAN_F8DATA0(canx) REG32((canx) + 0x280U) /*!< CAN filter 8 data 0 register */
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#define CAN_F9DATA0(canx) REG32((canx) + 0x288U) /*!< CAN filter 9 data 0 register */
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#define CAN_F10DATA0(canx) REG32((canx) + 0x290U) /*!< CAN filter 10 data 0 register */
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#define CAN_F11DATA0(canx) REG32((canx) + 0x298U) /*!< CAN filter 11 data 0 register */
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#define CAN_F12DATA0(canx) REG32((canx) + 0x2A0U) /*!< CAN filter 12 data 0 register */
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#define CAN_F13DATA0(canx) REG32((canx) + 0x2A8U) /*!< CAN filter 13 data 0 register */
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#define CAN_F14DATA0(canx) REG32((canx) + 0x2B0U) /*!< CAN filter 14 data 0 register */
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#define CAN_F15DATA0(canx) REG32((canx) + 0x2B8U) /*!< CAN filter 15 data 0 register */
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#define CAN_F16DATA0(canx) REG32((canx) + 0x2C0U) /*!< CAN filter 16 data 0 register */
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#define CAN_F17DATA0(canx) REG32((canx) + 0x2C8U) /*!< CAN filter 17 data 0 register */
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#define CAN_F18DATA0(canx) REG32((canx) + 0x2D0U) /*!< CAN filter 18 data 0 register */
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#define CAN_F19DATA0(canx) REG32((canx) + 0x2D8U) /*!< CAN filter 19 data 0 register */
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#define CAN_F20DATA0(canx) REG32((canx) + 0x2E0U) /*!< CAN filter 20 data 0 register */
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#define CAN_F21DATA0(canx) REG32((canx) + 0x2E8U) /*!< CAN filter 21 data 0 register */
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#define CAN_F22DATA0(canx) REG32((canx) + 0x2F0U) /*!< CAN filter 22 data 0 register */
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#define CAN_F23DATA0(canx) REG32((canx) + 0x3F8U) /*!< CAN filter 23 data 0 register */
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#define CAN_F24DATA0(canx) REG32((canx) + 0x300U) /*!< CAN filter 24 data 0 register */
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#define CAN_F25DATA0(canx) REG32((canx) + 0x308U) /*!< CAN filter 25 data 0 register */
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#define CAN_F26DATA0(canx) REG32((canx) + 0x310U) /*!< CAN filter 26 data 0 register */
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#define CAN_F27DATA0(canx) REG32((canx) + 0x318U) /*!< CAN filter 27 data 0 register */
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#define CAN_F0DATA1(canx) REG32((canx) + 0x244U) /*!< CAN filter 0 data 1 register */
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#define CAN_F1DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 1 data 1 register */
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#define CAN_F2DATA1(canx) REG32((canx) + 0x254U) /*!< CAN filter 2 data 1 register */
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#define CAN_F3DATA1(canx) REG32((canx) + 0x25CU) /*!< CAN filter 3 data 1 register */
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#define CAN_F4DATA1(canx) REG32((canx) + 0x264U) /*!< CAN filter 4 data 1 register */
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#define CAN_F5DATA1(canx) REG32((canx) + 0x26CU) /*!< CAN filter 5 data 1 register */
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#define CAN_F6DATA1(canx) REG32((canx) + 0x274U) /*!< CAN filter 6 data 1 register */
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#define CAN_F7DATA1(canx) REG32((canx) + 0x27CU) /*!< CAN filter 7 data 1 register */
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#define CAN_F8DATA1(canx) REG32((canx) + 0x284U) /*!< CAN filter 8 data 1 register */
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#define CAN_F9DATA1(canx) REG32((canx) + 0x28CU) /*!< CAN filter 9 data 1 register */
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#define CAN_F10DATA1(canx) REG32((canx) + 0x294U) /*!< CAN filter 10 data 1 register */
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#define CAN_F11DATA1(canx) REG32((canx) + 0x29CU) /*!< CAN filter 11 data 1 register */
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#define CAN_F12DATA1(canx) REG32((canx) + 0x2A4U) /*!< CAN filter 12 data 1 register */
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#define CAN_F13DATA1(canx) REG32((canx) + 0x2ACU) /*!< CAN filter 13 data 1 register */
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#define CAN_F14DATA1(canx) REG32((canx) + 0x2B4U) /*!< CAN filter 14 data 1 register */
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#define CAN_F15DATA1(canx) REG32((canx) + 0x2BCU) /*!< CAN filter 15 data 1 register */
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#define CAN_F16DATA1(canx) REG32((canx) + 0x2C4U) /*!< CAN filter 16 data 1 register */
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#define CAN_F17DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 17 data 1 register */
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#define CAN_F18DATA1(canx) REG32((canx) + 0x2D4U) /*!< CAN filter 18 data 1 register */
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#define CAN_F19DATA1(canx) REG32((canx) + 0x2DCU) /*!< CAN filter 19 data 1 register */
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#define CAN_F20DATA1(canx) REG32((canx) + 0x2E4U) /*!< CAN filter 20 data 1 register */
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#define CAN_F21DATA1(canx) REG32((canx) + 0x2ECU) /*!< CAN filter 21 data 1 register */
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#define CAN_F22DATA1(canx) REG32((canx) + 0x2F4U) /*!< CAN filter 22 data 1 register */
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#define CAN_F23DATA1(canx) REG32((canx) + 0x2FCU) /*!< CAN filter 23 data 1 register */
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#define CAN_F24DATA1(canx) REG32((canx) + 0x304U) /*!< CAN filter 24 data 1 register */
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#define CAN_F25DATA1(canx) REG32((canx) + 0x30CU) /*!< CAN filter 25 data 1 register */
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#define CAN_F26DATA1(canx) REG32((canx) + 0x314U) /*!< CAN filter 26 data 1 register */
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#define CAN_F27DATA1(canx) REG32((canx) + 0x31CU) /*!< CAN filter 27 data 1 register */
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/* CAN transmit mailbox bank */
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2021-06-09 16:24:20 +08:00
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#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */
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#define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */
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#define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */
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#define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */
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/* CAN filter bank */
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#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */
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#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */
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/* CAN receive fifo mailbox bank */
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#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */
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#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */
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#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */
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#define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */
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/* bits definitions */
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/* CAN_CTL */
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#define CAN_CTL_IWMOD BIT(0) /*!< initial working mode */
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#define CAN_CTL_SLPWMOD BIT(1) /*!< sleep working mode */
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#define CAN_CTL_TFO BIT(2) /*!< transmit FIFO order */
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#define CAN_CTL_RFOD BIT(3) /*!< receive FIFO overwrite disable */
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#define CAN_CTL_ARD BIT(4) /*!< automatic retransmission disable */
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#define CAN_CTL_AWU BIT(5) /*!< automatic wakeup */
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#define CAN_CTL_ABOR BIT(6) /*!< automatic bus-off recovery */
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#define CAN_CTL_TTC BIT(7) /*!< time triggered communication */
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#define CAN_CTL_SWRST BIT(15) /*!< CAN software reset */
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#define CAN_CTL_DFZ BIT(16) /*!< CAN debug freeze */
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/* CAN_STAT */
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#define CAN_STAT_IWS BIT(0) /*!< initial working state */
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#define CAN_STAT_SLPWS BIT(1) /*!< sleep working state */
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#define CAN_STAT_ERRIF BIT(2) /*!< error interrupt flag*/
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#define CAN_STAT_WUIF BIT(3) /*!< status change interrupt flag of wakeup from sleep working mode */
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#define CAN_STAT_SLPIF BIT(4) /*!< status change interrupt flag of sleep working mode entering */
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#define CAN_STAT_TS BIT(8) /*!< transmitting state */
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#define CAN_STAT_RS BIT(9) /*!< receiving state */
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#define CAN_STAT_LASTRX BIT(10) /*!< last sample value of rx pin */
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#define CAN_STAT_RXL BIT(11) /*!< CAN rx signal */
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/* CAN_TSTAT */
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#define CAN_TSTAT_MTF0 BIT(0) /*!< mailbox0 transmit finished */
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#define CAN_TSTAT_MTFNERR0 BIT(1) /*!< mailbox0 transmit finished and no error */
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#define CAN_TSTAT_MAL0 BIT(2) /*!< mailbox0 arbitration lost */
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#define CAN_TSTAT_MTE0 BIT(3) /*!< mailbox0 transmit error */
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#define CAN_TSTAT_MST0 BIT(7) /*!< mailbox0 stop transmitting */
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#define CAN_TSTAT_MTF1 BIT(8) /*!< mailbox1 transmit finished */
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#define CAN_TSTAT_MTFNERR1 BIT(9) /*!< mailbox1 transmit finished and no error */
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#define CAN_TSTAT_MAL1 BIT(10) /*!< mailbox1 arbitration lost */
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#define CAN_TSTAT_MTE1 BIT(11) /*!< mailbox1 transmit error */
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#define CAN_TSTAT_MST1 BIT(15) /*!< mailbox1 stop transmitting */
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#define CAN_TSTAT_MTF2 BIT(16) /*!< mailbox2 transmit finished */
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#define CAN_TSTAT_MTFNERR2 BIT(17) /*!< mailbox2 transmit finished and no error */
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#define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */
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#define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */
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#define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */
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#define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */
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#define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */
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#define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */
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#define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */
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#define CAN_TSTAT_TMLS0 BIT(29) /*!< last sending priority flag for mailbox0 */
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#define CAN_TSTAT_TMLS1 BIT(30) /*!< last sending priority flag for mailbox1 */
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#define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */
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/* CAN_RFIFO0 */
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#define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */
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#define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */
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#define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */
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#define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */
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/* CAN_RFIFO1 */
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#define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */
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#define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */
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#define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */
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#define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */
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/* CAN_INTEN */
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#define CAN_INTEN_TMEIE BIT(0) /*!< transmit mailbox empty interrupt enable */
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#define CAN_INTEN_RFNEIE0 BIT(1) /*!< receive FIFO0 not empty interrupt enable */
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#define CAN_INTEN_RFFIE0 BIT(2) /*!< receive FIFO0 full interrupt enable */
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#define CAN_INTEN_RFOIE0 BIT(3) /*!< receive FIFO0 overfull interrupt enable */
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#define CAN_INTEN_RFNEIE1 BIT(4) /*!< receive FIFO1 not empty interrupt enable */
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#define CAN_INTEN_RFFIE1 BIT(5) /*!< receive FIFO1 full interrupt enable */
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#define CAN_INTEN_RFOIE1 BIT(6) /*!< receive FIFO1 overfull interrupt enable */
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#define CAN_INTEN_WERRIE BIT(8) /*!< warning error interrupt enable */
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#define CAN_INTEN_PERRIE BIT(9) /*!< passive error interrupt enable */
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#define CAN_INTEN_BOIE BIT(10) /*!< bus-off interrupt enable */
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#define CAN_INTEN_ERRNIE BIT(11) /*!< error number interrupt enable */
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#define CAN_INTEN_ERRIE BIT(15) /*!< error interrupt enable */
|
2021-06-09 16:24:20 +08:00
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#define CAN_INTEN_WIE BIT(16) /*!< wakeup interrupt enable */
|
2017-08-22 15:52:57 +08:00
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#define CAN_INTEN_SLPWIE BIT(17) /*!< sleep working interrupt enable */
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/* CAN_ERR */
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#define CAN_ERR_WERR BIT(0) /*!< warning error */
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#define CAN_ERR_PERR BIT(1) /*!< passive error */
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#define CAN_ERR_BOERR BIT(2) /*!< bus-off error */
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#define CAN_ERR_ERRN BITS(4,6) /*!< error number */
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#define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */
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#define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */
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/* CAN_BT */
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#define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */
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#define CAN_BT_BS1 BITS(16,19) /*!< bit segment 1 */
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#define CAN_BT_BS2 BITS(20,22) /*!< bit segment 2 */
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#define CAN_BT_SJW BITS(24,25) /*!< resynchronization jump width */
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#define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */
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#define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */
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/* CAN_TMIx */
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#define CAN_TMI_TEN BIT(0) /*!< transmit enable */
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#define CAN_TMI_FT BIT(1) /*!< frame type */
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#define CAN_TMI_FF BIT(2) /*!< frame format */
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#define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */
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#define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */
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/* CAN_TMPx */
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#define CAN_TMP_DLENC BITS(0,3) /*!< data length code */
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#define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */
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#define CAN_TMP_TS BITS(16,31) /*!< time stamp */
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/* CAN_TMDATA0x */
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#define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */
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#define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */
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#define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */
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#define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */
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/* CAN_TMDATA1x */
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#define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */
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#define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */
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#define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */
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#define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */
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/* CAN_RFIFOMIx */
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#define CAN_RFIFOMI_FT BIT(1) /*!< frame type */
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#define CAN_RFIFOMI_FF BIT(2) /*!< frame format */
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#define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */
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#define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */
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/* CAN_RFIFOMPx */
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#define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */
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#define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */
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#define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */
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/* CAN_RFIFOMDATA0x */
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#define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */
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#define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */
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#define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */
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#define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */
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/* CAN_RFIFOMDATA1x */
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#define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */
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#define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */
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#define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */
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#define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */
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/* CAN_FCTL */
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#define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */
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#define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */
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/* CAN_FMCFG */
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#define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/
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/* CAN_FSCFG */
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#define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits*/
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/* CAN_FAFIFO */
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#define CAN_FAFIFOR_FAF(regval) BIT(regval) /*!< filter associated with FIFO */
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/* CAN_FW */
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#define CAN_FW_FW(regval) BIT(regval) /*!< filter working */
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|
2021-06-09 16:24:20 +08:00
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/* CAN_FxDATAy */
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#define CAN_FDATA_FD(regval) BIT(regval) /*!< filter data */
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|
2017-08-22 15:52:57 +08:00
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/* consts definitions */
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|
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/* define the CAN bit position and its register index offset */
|
2021-06-09 16:24:20 +08:00
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#define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
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#define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6)))
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#define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
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#define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1))
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#define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12)))
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#define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU)
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#define CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU)
|
2017-08-22 15:52:57 +08:00
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/* register offset */
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#define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */
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#define TSTAT_REG_OFFSET ((uint8_t)0x08U) /*!< TSTAT register offset */
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#define RFIFO0_REG_OFFSET ((uint8_t)0x0CU) /*!< RFIFO0 register offset */
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#define RFIFO1_REG_OFFSET ((uint8_t)0x10U) /*!< RFIFO1 register offset */
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#define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */
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/* CAN flags */
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|
|
typedef enum
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{
|
2021-06-09 16:24:20 +08:00
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/* flags in STAT register */
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CAN_FLAG_RXL = CAN_REGIDX_BIT(STAT_REG_OFFSET, 11U), /*!< RX level */
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CAN_FLAG_LASTRX = CAN_REGIDX_BIT(STAT_REG_OFFSET, 10U), /*!< last sample value of RX pin */
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CAN_FLAG_RS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 9U), /*!< receiving state */
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CAN_FLAG_TS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 8U), /*!< transmitting state */
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CAN_FLAG_SLPIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 4U), /*!< status change flag of entering sleep working mode */
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CAN_FLAG_WUIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 3U), /*!< status change flag of wakeup from sleep working mode */
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CAN_FLAG_ERRIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 2U), /*!< error flag */
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CAN_FLAG_SLPWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 1U), /*!< sleep working state */
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CAN_FLAG_IWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 0U), /*!< initial working state */
|
2017-08-22 15:52:57 +08:00
|
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/* flags in TSTAT register */
|
2021-06-09 16:24:20 +08:00
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CAN_FLAG_TMLS2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 31U), /*!< transmit mailbox 2 last sending in Tx FIFO */
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CAN_FLAG_TMLS1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 30U), /*!< transmit mailbox 1 last sending in Tx FIFO */
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CAN_FLAG_TMLS0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 29U), /*!< transmit mailbox 0 last sending in Tx FIFO */
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CAN_FLAG_TME2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 28U), /*!< transmit mailbox 2 empty */
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CAN_FLAG_TME1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 27U), /*!< transmit mailbox 1 empty */
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CAN_FLAG_TME0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 26U), /*!< transmit mailbox 0 empty */
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CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */
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|
CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */
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CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */
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CAN_FLAG_MAL2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 18U), /*!< mailbox 2 arbitration lost */
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|
|
CAN_FLAG_MAL1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 10U), /*!< mailbox 1 arbitration lost */
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|
|
CAN_FLAG_MAL0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 2U), /*!< mailbox 0 arbitration lost */
|
|
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|
|
CAN_FLAG_MTFNERR2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 17U), /*!< mailbox 2 transmit finished with no error */
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|
|
|
|
CAN_FLAG_MTFNERR1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 9U), /*!< mailbox 1 transmit finished with no error */
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|
|
CAN_FLAG_MTFNERR0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 1U), /*!< mailbox 0 transmit finished with no error */
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|
|
CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */
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|
|
CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */
|
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|
|
CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */
|
2017-08-22 15:52:57 +08:00
|
|
|
/* flags in RFIFO0 register */
|
2021-06-09 16:24:20 +08:00
|
|
|
CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */
|
|
|
|
|
CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */
|
2017-08-22 15:52:57 +08:00
|
|
|
/* flags in RFIFO1 register */
|
2021-06-09 16:24:20 +08:00
|
|
|
CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */
|
|
|
|
|
CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */
|
2017-08-22 15:52:57 +08:00
|
|
|
/* flags in ERR register */
|
2021-06-09 16:24:20 +08:00
|
|
|
CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */
|
|
|
|
|
CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */
|
|
|
|
|
CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */
|
2017-08-22 15:52:57 +08:00
|
|
|
}can_flag_enum;
|
|
|
|
|
|
|
|
|
|
/* CAN interrupt flags */
|
|
|
|
|
typedef enum
|
|
|
|
|
{
|
|
|
|
|
/* interrupt flags in STAT register */
|
2021-06-09 16:24:20 +08:00
|
|
|
CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */
|
|
|
|
|
CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */
|
|
|
|
|
CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */
|
|
|
|
|
/* interrupt flags in TSTAT register */
|
|
|
|
|
CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */
|
|
|
|
|
CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */
|
|
|
|
|
CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U), /*!< mailbox 0 transmit finished interrupt flag */
|
|
|
|
|
/* interrupt flags in RFIFO0 register */
|
|
|
|
|
CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U), /*!< receive FIFO0 overfull interrupt flag */
|
|
|
|
|
CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U), /*!< receive FIFO0 full interrupt flag */
|
|
|
|
|
CAN_INT_FLAG_RFL0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 2U, 1U), /*!< receive FIFO0 not empty interrupt flag */
|
|
|
|
|
/* interrupt flags in RFIFO0 register */
|
|
|
|
|
CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */
|
|
|
|
|
CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */
|
|
|
|
|
CAN_INT_FLAG_RFL1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 2U, 4U), /*!< receive FIFO0 not empty interrupt flag */
|
|
|
|
|
/* interrupt flags in ERR register */
|
|
|
|
|
CAN_INT_FLAG_ERRN = CAN_REGIDX_BITS(ERR_REG_OFFSET, 3U, 11U), /*!< error number interrupt flag */
|
|
|
|
|
CAN_INT_FLAG_BOERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 2U, 10U), /*!< bus-off error interrupt flag */
|
|
|
|
|
CAN_INT_FLAG_PERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 1U, 9U), /*!< passive error interrupt flag */
|
|
|
|
|
CAN_INT_FLAG_WERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 0U, 8U), /*!< warning error interrupt flag */
|
2017-08-22 15:52:57 +08:00
|
|
|
}can_interrupt_flag_enum;
|
|
|
|
|
|
|
|
|
|
/* CAN initiliaze parameters struct */
|
|
|
|
|
typedef struct
|
|
|
|
|
{
|
2021-06-09 16:24:20 +08:00
|
|
|
uint8_t working_mode; /*!< CAN working mode */
|
2017-08-22 15:52:57 +08:00
|
|
|
uint8_t resync_jump_width; /*!< CAN resynchronization jump width */
|
|
|
|
|
uint8_t time_segment_1; /*!< time segment 1 */
|
|
|
|
|
uint8_t time_segment_2; /*!< time segment 2 */
|
|
|
|
|
ControlStatus time_triggered; /*!< time triggered communication mode */
|
|
|
|
|
ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */
|
|
|
|
|
ControlStatus auto_wake_up; /*!< automatic wake-up mode */
|
2021-06-09 16:24:20 +08:00
|
|
|
ControlStatus no_auto_retrans; /*!< automatic retransmission mode disable */
|
2017-08-22 15:52:57 +08:00
|
|
|
ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */
|
|
|
|
|
ControlStatus trans_fifo_order; /*!< transmit FIFO order */
|
|
|
|
|
uint16_t prescaler; /*!< baudrate prescaler */
|
|
|
|
|
}can_parameter_struct;
|
|
|
|
|
|
|
|
|
|
/* CAN transmit message struct */
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typedef struct
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{
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uint32_t tx_sfid; /*!< standard format frame identifier */
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uint32_t tx_efid; /*!< extended format frame identifier */
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uint8_t tx_ff; /*!< format of frame, standard or extended format */
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uint8_t tx_ft; /*!< type of frame, data or remote */
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uint8_t tx_dlen; /*!< data length */
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uint8_t tx_data[8]; /*!< transmit data */
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}can_trasnmit_message_struct;
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/* CAN receive message struct */
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typedef struct
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{
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uint32_t rx_sfid; /*!< standard format frame identifier */
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uint32_t rx_efid; /*!< extended format frame identifier */
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uint8_t rx_ff; /*!< format of frame, standard or extended format */
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uint8_t rx_ft; /*!< type of frame, data or remote */
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uint8_t rx_dlen; /*!< data length */
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uint8_t rx_data[8]; /*!< receive data */
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uint8_t rx_fi; /*!< filtering index */
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} can_receive_message_struct;
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/* CAN filter parameters struct */
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typedef struct
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{
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uint16_t filter_list_high; /*!< filter list number high bits*/
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uint16_t filter_list_low; /*!< filter list number low bits */
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uint16_t filter_mask_high; /*!< filter mask number high bits */
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uint16_t filter_mask_low; /*!< filter mask number low bits */
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uint16_t filter_fifo_number; /*!< receive FIFO associated with the filter */
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uint16_t filter_number; /*!< filter number */
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uint16_t filter_mode; /*!< filter mode, list or mask */
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uint16_t filter_bits; /*!< filter scale */
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ControlStatus filter_enable; /*!< filter work or not */
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}can_filter_parameter_struct;
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/* CAN errors */
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typedef enum
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{
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CAN_ERROR_NONE = 0, /*!< no error */
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CAN_ERROR_FILL, /*!< fill error */
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CAN_ERROR_FORMATE, /*!< format error */
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CAN_ERROR_ACK, /*!< ACK error */
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CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */
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CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */
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CAN_ERROR_CRC, /*!< CRC error */
|
2021-06-09 16:24:20 +08:00
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CAN_ERROR_SOFTWARECFG, /*!< software configure */
|
2017-08-22 15:52:57 +08:00
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}can_error_enum;
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/* transmit states */
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typedef enum
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{
|
2021-06-09 16:24:20 +08:00
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CAN_TRANSMIT_FAILED = 0U, /*!< CAN transmitted failure */
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CAN_TRANSMIT_OK = 1U, /*!< CAN transmitted success */
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CAN_TRANSMIT_PENDING = 2U, /*!< CAN transmitted pending */
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CAN_TRANSMIT_NOMAILBOX = 4U, /*!< no empty mailbox to be used for CAN */
|
2017-08-22 15:52:57 +08:00
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}can_transmit_state_enum;
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2021-06-09 16:24:20 +08:00
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typedef enum
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{
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CAN_INIT_STRUCT = 0, /* CAN initiliaze parameters struct */
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CAN_FILTER_STRUCT, /* CAN filter parameters struct */
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CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */
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CAN_RX_MESSAGE_STRUCT, /* CAN receive message struct */
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}can_struct_type_enum;
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2017-08-22 15:52:57 +08:00
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/* CAN baudrate prescaler*/
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#define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0))
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/* CAN bit segment 1*/
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#define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16))
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/* CAN bit segment 2*/
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#define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20))
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/* CAN resynchronization jump width*/
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#define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24))
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/* CAN communication mode*/
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#define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30))
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/* CAN FDATA high 16 bits */
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#define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16))
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/* CAN FDATA low 16 bits */
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#define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
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/* CAN1 filter start bank_number*/
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#define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8))
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/* CAN transmit mailbox extended identifier*/
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#define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3))
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/* CAN transmit mailbox standard identifier*/
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#define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21))
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/* transmit data byte 0 */
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#define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
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/* transmit data byte 1 */
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#define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8))
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/* transmit data byte 2 */
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#define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16))
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|
2021-06-09 16:24:20 +08:00
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/* transmit data byte 3 */
|
2017-08-22 15:52:57 +08:00
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#define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24))
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|
2021-06-09 16:24:20 +08:00
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/* transmit data byte 4 */
|
2017-08-22 15:52:57 +08:00
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#define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
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|
2021-06-09 16:24:20 +08:00
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/* transmit data byte 5 */
|
2017-08-22 15:52:57 +08:00
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#define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8))
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|
2021-06-09 16:24:20 +08:00
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/* transmit data byte 6 */
|
2017-08-22 15:52:57 +08:00
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#define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16))
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|
2021-06-09 16:24:20 +08:00
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/* transmit data byte 7 */
|
2017-08-22 15:52:57 +08:00
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#define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24))
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/* receive mailbox extended identifier*/
|
2021-06-09 16:24:20 +08:00
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#define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3U, 31U)
|
2017-08-22 15:52:57 +08:00
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/* receive mailbox standrad identifier*/
|
2021-06-09 16:24:20 +08:00
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#define GET_RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21U, 31U)
|
2017-08-22 15:52:57 +08:00
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/* receive data length */
|
2021-06-09 16:24:20 +08:00
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#define GET_RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0U, 3U)
|
2017-08-22 15:52:57 +08:00
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|
2021-06-09 16:24:20 +08:00
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/* the index of the filter by which the frame is passed */
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#define GET_RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8U, 15U)
|
2017-08-22 15:52:57 +08:00
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/* receive data byte 0 */
|
2021-06-09 16:24:20 +08:00
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#define GET_RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0U, 7U)
|
2017-08-22 15:52:57 +08:00
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/* receive data byte 1 */
|
2021-06-09 16:24:20 +08:00
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#define GET_RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8U, 15U)
|
2017-08-22 15:52:57 +08:00
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/* receive data byte 2 */
|
2021-06-09 16:24:20 +08:00
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#define GET_RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16U, 23U)
|
2017-08-22 15:52:57 +08:00
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|
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/* receive data byte 3 */
|
2021-06-09 16:24:20 +08:00
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|
|
#define GET_RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24U, 31U)
|
2017-08-22 15:52:57 +08:00
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/* receive data byte 4 */
|
2021-06-09 16:24:20 +08:00
|
|
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#define GET_RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0U, 7U)
|
2017-08-22 15:52:57 +08:00
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|
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/* receive data byte 5 */
|
2021-06-09 16:24:20 +08:00
|
|
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#define GET_RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8U, 15U)
|
2017-08-22 15:52:57 +08:00
|
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|
|
/* receive data byte 6 */
|
2021-06-09 16:24:20 +08:00
|
|
|
#define GET_RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16U, 23U)
|
2017-08-22 15:52:57 +08:00
|
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|
|
|
|
/* receive data byte 7 */
|
2021-06-09 16:24:20 +08:00
|
|
|
#define GET_RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24U, 31U)
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|
|
/* error number */
|
|
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|
|
#define GET_ERR_ERRN(regval) GET_BITS((uint32_t)(regval), 4U, 6U)
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|
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/* transmit error count */
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|
|
#define GET_ERR_TECNT(regval) GET_BITS((uint32_t)(regval), 16U, 23U)
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|
|
/* receive error count */
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|
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|
|
#define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24U, 31U)
|
2017-08-22 15:52:57 +08:00
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|
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/* CAN errors */
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|
|
#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4))
|
2021-06-09 16:24:20 +08:00
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|
#define CAN_ERRN_0 ERR_ERRN(0U) /* no error */
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#define CAN_ERRN_1 ERR_ERRN(1U) /*!< fill error */
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#define CAN_ERRN_2 ERR_ERRN(2U) /*!< format error */
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#define CAN_ERRN_3 ERR_ERRN(3U) /*!< ACK error */
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|
#define CAN_ERRN_4 ERR_ERRN(4U) /*!< bit recessive error */
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|
#define CAN_ERRN_5 ERR_ERRN(5U) /*!< bit dominant error */
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|
#define CAN_ERRN_6 ERR_ERRN(6U) /*!< CRC error */
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#define CAN_ERRN_7 ERR_ERRN(7U) /*!< software error */
|
2017-08-22 15:52:57 +08:00
|
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|
|
#define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */
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|
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/* CAN communication mode */
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|
|
#define CAN_NORMAL_MODE ((uint8_t)0x00U) /*!< normal communication mode */
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|
|
#define CAN_LOOPBACK_MODE ((uint8_t)0x01U) /*!< loopback communication mode */
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|
|
#define CAN_SILENT_MODE ((uint8_t)0x02U) /*!< silent communication mode */
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|
|
#define CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U) /*!< loopback and silent communication mode */
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|
|
/* CAN resynchronisation jump width */
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|
|
|
|
#define CAN_BT_SJW_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */
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|
|
#define CAN_BT_SJW_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */
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|
|
#define CAN_BT_SJW_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */
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#define CAN_BT_SJW_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */
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|
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/* CAN time segment 1 */
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|
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|
|
#define CAN_BT_BS1_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */
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#define CAN_BT_BS1_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */
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|
|
#define CAN_BT_BS1_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */
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|
#define CAN_BT_BS1_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */
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|
|
#define CAN_BT_BS1_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */
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|
|
#define CAN_BT_BS1_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */
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|
|
#define CAN_BT_BS1_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */
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|
|
#define CAN_BT_BS1_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */
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|
|
|
#define CAN_BT_BS1_9TQ ((uint8_t)0x08U) /*!< 9 time quanta */
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|
|
|
|
#define CAN_BT_BS1_10TQ ((uint8_t)0x09U) /*!< 10 time quanta */
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|
|
|
|
#define CAN_BT_BS1_11TQ ((uint8_t)0x0AU) /*!< 11 time quanta */
|
|
|
|
|
#define CAN_BT_BS1_12TQ ((uint8_t)0x0BU) /*!< 12 time quanta */
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|
|
|
|
#define CAN_BT_BS1_13TQ ((uint8_t)0x0CU) /*!< 13 time quanta */
|
|
|
|
|
#define CAN_BT_BS1_14TQ ((uint8_t)0x0DU) /*!< 14 time quanta */
|
|
|
|
|
#define CAN_BT_BS1_15TQ ((uint8_t)0x0EU) /*!< 15 time quanta */
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|
|
|
|
#define CAN_BT_BS1_16TQ ((uint8_t)0x0FU) /*!< 16 time quanta */
|
|
|
|
|
|
|
|
|
|
/* CAN time segment 2 */
|
|
|
|
|
#define CAN_BT_BS2_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */
|
|
|
|
|
#define CAN_BT_BS2_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */
|
|
|
|
|
#define CAN_BT_BS2_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */
|
|
|
|
|
#define CAN_BT_BS2_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */
|
|
|
|
|
#define CAN_BT_BS2_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */
|
|
|
|
|
#define CAN_BT_BS2_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */
|
|
|
|
|
#define CAN_BT_BS2_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */
|
|
|
|
|
#define CAN_BT_BS2_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */
|
|
|
|
|
|
|
|
|
|
/* CAN mailbox number */
|
|
|
|
|
#define CAN_MAILBOX0 ((uint8_t)0x00U) /*!< mailbox0 */
|
|
|
|
|
#define CAN_MAILBOX1 ((uint8_t)0x01U) /*!< mailbox1 */
|
|
|
|
|
#define CAN_MAILBOX2 ((uint8_t)0x02U) /*!< mailbox2 */
|
|
|
|
|
#define CAN_NOMAILBOX ((uint8_t)0x03U) /*!< no mailbox empty */
|
|
|
|
|
|
|
|
|
|
/* CAN frame format */
|
|
|
|
|
#define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */
|
|
|
|
|
#define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */
|
|
|
|
|
|
|
|
|
|
/* CAN receive fifo */
|
|
|
|
|
#define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */
|
|
|
|
|
#define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */
|
|
|
|
|
|
|
|
|
|
/* frame number of receive fifo */
|
2021-06-09 16:24:20 +08:00
|
|
|
#define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */
|
2017-08-22 15:52:57 +08:00
|
|
|
|
|
|
|
|
#define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */
|
|
|
|
|
#define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU) /*!< mask of extended identifier */
|
|
|
|
|
|
|
|
|
|
/* CAN working mode */
|
|
|
|
|
#define CAN_MODE_INITIALIZE ((uint8_t)0x01U) /*!< CAN initialize mode */
|
|
|
|
|
#define CAN_MODE_NORMAL ((uint8_t)0x02U) /*!< CAN normal mode */
|
|
|
|
|
#define CAN_MODE_SLEEP ((uint8_t)0x04U) /*!< CAN sleep mode */
|
|
|
|
|
|
|
|
|
|
/* filter bits */
|
|
|
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#define CAN_FILTERBITS_16BIT ((uint8_t)0x00U) /*!< CAN filter 16 bits */
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#define CAN_FILTERBITS_32BIT ((uint8_t)0x01U) /*!< CAN filter 32 bits */
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/* filter mode */
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#define CAN_FILTERMODE_MASK ((uint8_t)0x00U) /*!< mask mode */
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#define CAN_FILTERMODE_LIST ((uint8_t)0x01U) /*!< list mode */
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/* filter 16 bits mask */
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#define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU) /*!< can filter 16 bits mask */
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/* frame type */
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#define CAN_FT_DATA ((uint32_t)0x00000000U) /*!< data frame */
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#define CAN_FT_REMOTE ((uint32_t)0x00000002U) /*!< remote frame */
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/* CAN timeout */
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#define CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */
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/* interrupt enable bits */
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#define CAN_INT_TME CAN_INTEN_TMEIE /*!< transmit mailbox empty interrupt enable */
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#define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0 /*!< receive FIFO0 not empty interrupt enable */
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#define CAN_INT_RFF0 CAN_INTEN_RFFIE0 /*!< receive FIFO0 full interrupt enable */
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#define CAN_INT_RFO0 CAN_INTEN_RFOIE0 /*!< receive FIFO0 overfull interrupt enable */
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#define CAN_INT_RFNE1 CAN_INTEN_RFNEIE1 /*!< receive FIFO1 not empty interrupt enable */
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#define CAN_INT_RFF1 CAN_INTEN_RFFIE1 /*!< receive FIFO1 full interrupt enable */
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#define CAN_INT_RFO1 CAN_INTEN_RFOIE1 /*!< receive FIFO1 overfull interrupt enable */
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#define CAN_INT_WERR CAN_INTEN_WERRIE /*!< warning error interrupt enable */
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#define CAN_INT_PERR CAN_INTEN_PERRIE /*!< passive error interrupt enable */
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#define CAN_INT_BO CAN_INTEN_BOIE /*!< bus-off interrupt enable */
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#define CAN_INT_ERRN CAN_INTEN_ERRNIE /*!< error number interrupt enable */
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#define CAN_INT_ERR CAN_INTEN_ERRIE /*!< error interrupt enable */
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#define CAN_INT_WAKEUP CAN_INTEN_WIE /*!< wakeup interrupt enable */
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#define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */
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2017-08-22 15:52:57 +08:00
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/* function declarations */
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/* deinitialize CAN */
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void can_deinit(uint32_t can_periph);
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/* initialize CAN struct */
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void can_struct_para_init(can_struct_type_enum type, void* p_struct);
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/* initialize CAN */
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ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init);
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/* CAN filter init */
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void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init);
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/* set can1 fliter start bank number */
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void can1_filter_start_bank(uint8_t start_bank);
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/* enable functions */
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/* CAN debug freeze enable */
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void can_debug_freeze_enable(uint32_t can_periph);
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/* CAN debug freeze disable */
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void can_debug_freeze_disable(uint32_t can_periph);
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/* CAN time trigger mode enable */
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void can_time_trigger_mode_enable(uint32_t can_periph);
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/* CAN time trigger mode disable */
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void can_time_trigger_mode_disable(uint32_t can_periph);
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/* transmit functions */
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/* transmit CAN message */
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uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message);
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/* get CAN transmit state */
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can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number);
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/* stop CAN transmission */
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void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number);
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/* CAN receive message */
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void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message);
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/* CAN release fifo */
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void can_fifo_release(uint32_t can_periph, uint8_t fifo_number);
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/* CAN receive message length */
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uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number);
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/* CAN working mode */
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ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode);
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/* CAN wakeup from sleep mode */
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ErrStatus can_wakeup(uint32_t can_periph);
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/* CAN get error */
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can_error_enum can_error_get(uint32_t can_periph);
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2021-06-09 16:24:20 +08:00
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/* get CAN receive error number */
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uint8_t can_receive_error_number_get(uint32_t can_periph);
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/* get CAN transmit error number */
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uint8_t can_transmit_error_number_get(uint32_t can_periph);
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/* CAN interrupt enable */
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void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt);
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/* CAN interrupt disable */
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void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt);
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2017-08-22 15:52:57 +08:00
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/* CAN get flag state */
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FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag);
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/* CAN clear flag state */
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void can_flag_clear(uint32_t can_periph, can_flag_enum flag);
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/* CAN get interrupt flag state */
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FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag);
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/* CAN clear interrupt flag state */
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void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag);
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#endif /* GD32F4XX_CAN_H */
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