2021-09-21 14:56:40 +08:00
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2017-06-05 tanek first implementation.
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2021-09-21 16:15:53 +08:00
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* 2018-04-19 misonyo Porting for v85xxf30x
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* 2019-03-31 xuzhuoyi Porting for v85xxe230
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* 2021-09-21 zhuxw Porting for v85xx
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2021-09-21 14:56:40 +08:00
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*/
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#include "drv_spi.h"
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#include "board.h"
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#include <rtthread.h>
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#if defined(RT_USING_SPI) && defined(RT_USING_PIN)
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#include <rtdevice.h>
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2021-09-21 16:15:53 +08:00
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#if !defined(RT_USING_SPI1) && !defined(RT_USING_SPI2)
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2021-09-21 14:56:40 +08:00
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#error "Please define at least one SPIx"
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#endif
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/* private rt-thread spi ops function */
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static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration);
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static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message);
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2021-09-21 16:15:53 +08:00
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static struct rt_spi_ops v85xx_spi_ops =
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2021-09-21 14:56:40 +08:00
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{
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configure,
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xfer
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};
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static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration)
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{
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2021-09-21 16:15:53 +08:00
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SPI_InitType spi_init_struct;
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2021-09-21 14:56:40 +08:00
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rt_uint32_t spi_periph = (rt_uint32_t)device->bus->parent.user_data;
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(configuration != RT_NULL);
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2021-09-21 16:15:53 +08:00
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if(configuration->data_width > 8)
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2021-09-21 14:56:40 +08:00
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{
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return RT_EIO;
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}
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{
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rt_uint32_t spi_apb_clock;
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rt_uint32_t max_hz;
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max_hz = configuration->max_hz;
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2021-09-21 16:15:53 +08:00
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spi_apb_clock = CLK_GetPCLKFreq();
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2021-09-21 14:56:40 +08:00
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if(max_hz >= spi_apb_clock/2)
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{
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2021-09-21 16:15:53 +08:00
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spi_init_struct.ClockDivision = SPI_CLKDIV_2;
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2021-09-21 14:56:40 +08:00
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}
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else if (max_hz >= spi_apb_clock/4)
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{
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2021-09-21 16:15:53 +08:00
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spi_init_struct.ClockDivision = SPI_CLKDIV_4;
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2021-09-21 14:56:40 +08:00
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}
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else if (max_hz >= spi_apb_clock/8)
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{
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2021-09-21 16:15:53 +08:00
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spi_init_struct.ClockDivision = SPI_CLKDIV_8;
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2021-09-21 14:56:40 +08:00
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}
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else if (max_hz >= spi_apb_clock/16)
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{
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spi_init_struct.ClockDivision = SPI_CLKDIV_16;
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}
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else if (max_hz >= spi_apb_clock/32)
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{
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spi_init_struct.ClockDivision = SPI_CLKDIV_32;
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2021-09-21 14:56:40 +08:00
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}
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else if (max_hz >= spi_apb_clock/64)
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{
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spi_init_struct.ClockDivision = SPI_CLKDIV_64;
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}
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else
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{
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2021-09-21 16:15:53 +08:00
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/* min prescaler 128 */
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spi_init_struct.ClockDivision = SPI_CLKDIV_128;
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2021-09-21 14:56:40 +08:00
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}
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} /* baudrate */
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switch(configuration->mode & RT_SPI_MODE_3)
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{
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case RT_SPI_MODE_0:
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2021-09-21 16:15:53 +08:00
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spi_init_struct.SPH = SPI_SPH_0;
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spi_init_struct.SPO = SPI_SPO_0;
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break;
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case RT_SPI_MODE_1:
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spi_init_struct.SPH = SPI_SPH_1;
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spi_init_struct.SPO = SPI_SPO_0;
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break;
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case RT_SPI_MODE_2:
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spi_init_struct.SPH = SPI_SPH_0;
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spi_init_struct.SPO = SPI_SPO_1;
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break;
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case RT_SPI_MODE_3:
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2021-09-21 16:15:53 +08:00
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spi_init_struct.SPH = SPI_SPH_1;
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spi_init_struct.SPO = SPI_SPO_1;
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break;
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}
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2021-09-21 16:15:53 +08:00
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if(!(configuration->mode & RT_SPI_MSB))
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{
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2021-09-21 16:15:53 +08:00
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return RT_EIO;
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}
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2021-09-21 16:15:53 +08:00
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spi_init_struct.Mode = SPI_MODE_MASTER;
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spi_init_struct.CSNSoft = SPI_CSNSOFT_ENABLE;
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2021-09-21 14:56:40 +08:00
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2021-09-21 16:15:53 +08:00
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SPI_Init((SPI_TypeDef*)spi_periph, &spi_init_struct);
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2021-09-21 14:56:40 +08:00
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2021-09-21 16:15:53 +08:00
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SPI_Cmd((SPI_TypeDef*)spi_periph, ENABLE);
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2021-09-21 14:56:40 +08:00
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return RT_EOK;
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};
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static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message)
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{
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rt_base_t v85xx_cs_pin = (rt_base_t)device->parent.user_data;
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rt_uint32_t spi_periph = (rt_uint32_t)device->bus->parent.user_data;
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struct rt_spi_configuration * config = &device->config;
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RT_ASSERT(device != NULL);
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RT_ASSERT(message != NULL);
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/* take CS */
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if(message->cs_take)
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{
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rt_pin_write(v85xx_cs_pin, PIN_LOW);
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DEBUG_PRINTF("spi take cs\n");
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}
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{
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if(config->data_width <= 8)
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{
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const rt_uint8_t * send_ptr = message->send_buf;
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rt_uint8_t * recv_ptr = message->recv_buf;
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rt_uint32_t size = message->length;
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DEBUG_PRINTF("spi poll transfer start: %d\n", size);
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while(size--)
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{
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rt_uint8_t data = 0xFF;
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if(send_ptr != RT_NULL)
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{
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data = *send_ptr++;
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}
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//Wait until the transmit buffer is empty
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while(RESET == SPI_GetStatus((SPI_TypeDef*)spi_periph, SPI_STS_TXEMPTY));
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// Send the byte
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SPI_SendData((SPI_TypeDef*)spi_periph, data);
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//Wait until a data is received
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while(RESET == SPI_GetStatus((SPI_TypeDef*)spi_periph, SPI_STS_RNE));
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// Get the received data
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data = SPI_ReceiveData((SPI_TypeDef*)spi_periph);
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if(recv_ptr != RT_NULL)
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{
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*recv_ptr++ = data;
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}
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}
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DEBUG_PRINTF("spi poll transfer finsh\n");
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}
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}
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/* release CS */
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if(message->cs_release)
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{
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2021-09-21 16:15:53 +08:00
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rt_pin_write(v85xx_cs_pin, PIN_HIGH);
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2021-09-21 14:56:40 +08:00
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DEBUG_PRINTF("spi release cs\n");
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}
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return message->length;
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};
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2021-09-21 16:15:53 +08:00
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int v85xx_hw_spi_init(void)
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{
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int result = 0;
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2021-09-21 16:15:53 +08:00
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#ifdef RT_USING_SPI1
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static struct rt_spi_bus spi_bus0;
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2021-09-21 16:15:53 +08:00
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spi_bus0.parent.user_data = (void *)SPI1;
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2021-09-21 14:56:40 +08:00
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2021-09-21 16:15:53 +08:00
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result = rt_spi_bus_register(&spi_bus0, "spi1", &v85xx_spi_ops);
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2021-09-21 14:56:40 +08:00
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2021-09-21 16:24:18 +08:00
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#endif
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2021-09-21 16:15:53 +08:00
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#ifdef RT_USING_SPI2
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static struct rt_spi_bus spi_bus1;
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spi_bus1.parent.user_data = (void *)SPI2;
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2021-09-21 14:56:40 +08:00
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2021-09-21 16:15:53 +08:00
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result = rt_spi_bus_register(&spi_bus1, "spi2", &v85xx_spi_ops);
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#endif
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return result;
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}
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INIT_BOARD_EXPORT(v85xx_hw_spi_init);
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2021-09-21 14:56:40 +08:00
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#endif
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