rt-thread-official/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt.ld

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/*
* Copyright 2021 - 2022 hpmicro
* SPDX-License-Identifier: BSD-3-Clause
*/
ENTRY(_start)
STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000;
HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M;
FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M;
SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M;
NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M;
MEMORY
{
XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE
ILM (wx) : ORIGIN = 0, LENGTH = 256K
DLM (w) : ORIGIN = 0x80000, LENGTH = 256K
AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1536K
SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE
SDRAM_NONCACHEABLE (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE
}
__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400;
__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000;
__app_load_addr__ = ORIGIN(XPI0) + 0x3000;
__boot_header_length__ = __boot_header_end__ - __boot_header_start__;
__app_offset__ = __app_load_addr__ - __boot_header_load_addr__;
SECTIONS
{
.nor_cfg_option __nor_cfg_option_load_addr__ : {
KEEP(*(.nor_cfg_option))
} > XPI0
.boot_header __boot_header_load_addr__ : {
__boot_header_start__ = .;
KEEP(*(.boot_header))
KEEP(*(.fw_info_table))
KEEP(*(.dc_info))
__boot_header_end__ = .;
} > XPI0
.start __app_load_addr__ : {
. = ALIGN(8);
KEEP(*(.start))
} > XPI0
__vector_load_addr__ = ADDR(.start) + SIZEOF(.start);
.vectors : AT(__vector_load_addr__) {
. = ALIGN(8);
__vector_ram_start__ = .;
KEEP(*(.vector_table))
KEEP(*(.isr_vector))
. = ALIGN(8);
__vector_ram_end__ = .;
} > AXI_SRAM
.fast : AT(etext + __data_end__ - __data_start__) {
. = ALIGN(8);
__ramfunc_start__ = .;
*(.fast)
/* RT-Thread Core Start */
KEEP(*context_gcc.o(.text* .rodata*))
KEEP(*cpuport.o (.text .text* .rodata .rodata*))
KEEP(*trap_entry.o (.text .text* .rodata .rodata*))
KEEP(*irq.o (.text .text* .rodata .rodata*))
KEEP(*clock.o (.text .text* .rodata .rodata*))
KEEP(*kservice.o (.text .text* .rodata .rodata*))
KEEP(*scheduler.o (.text .text* .rodata .rodata*))
KEEP(*trap.o (.text .text* .rodata .rodata*))
KEEP(*idle.o (.text .text* .rodata .rodata*))
KEEP(*ipc.o (.text .text* .rodata .rodata*))
KEEP(*thread.o (.text .text* .rodata .rodata*))
KEEP(*object.o (.text .text* .rodata .rodata*))
KEEP(*timer.o (.text .text* .rodata .rodata*))
KEEP(*mem.o (.text .text* .rodata .rodata*))
KEEP(*mempool.o (.text .text* .rodata .rodata*))
/* RT-Thread Core End */
. = ALIGN(8);
__ramfunc_end__ = .;
} > AXI_SRAM
.text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : {
. = ALIGN(8);
*(.text)
*(.text*)
*(.rodata)
*(.rodata*)
*(.srodata)
*(.srodata*)
*(.hash)
*(.dyn*)
*(.gnu*)
*(.pl*)
KEEP(*(.eh_frame))
*(.eh_frame*)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(8);
/*********************************************
*
* RT-Thread related sections - Start
*
*********************************************/
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
/* section information for modules */
. = ALIGN(4);
__rtmsymtab_start = .;
KEEP(*(RTMSymTab))
__rtmsymtab_end = .;
/* RT-Thread related sections - end */
} > XPI0
.rel : {
KEEP(*(.rel*))
} > XPI0
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
.data : AT(etext) {
. = ALIGN(8);
__data_start__ = .;
__global_pointer$ = . + 0x800;
*(.data)
*(.data*)
*(.sdata)
*(.sdata*)
*(.tdata)
*(.tdata*)
KEEP(*(.jcr))
KEEP(*(.dynamic))
KEEP(*(.got*))
KEEP(*(.got))
KEEP(*(.gcc_except_table))
KEEP(*(.gcc_except_table.*))
. = ALIGN(8);
PROVIDE(__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE(__preinit_array_end = .);
. = ALIGN(8);
PROVIDE(__init_array_start = .);
KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*)))
KEEP(*(.init_array))
PROVIDE(__init_array_end = .);
. = ALIGN(8);
PROVIDE(__finit_array_start = .);
KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
KEEP(*(.finit_array))
PROVIDE(__finit_array_end = .);
. = ALIGN(8);
KEEP(*crtbegin*.o(.ctors))
KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors))
KEEP(*(SORT(.ctors.*)))
KEEP(*(.ctors))
. = ALIGN(8);
KEEP(*crtbegin*.o(.dtors))
KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors))
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
. = ALIGN(8);
__data_end__ = .;
PROVIDE (__edata = .);
PROVIDE (_edata = .);
PROVIDE (edata = .);
} > SDRAM
__fw_size__ = __data_end__ - __data_start__ + etext - __app_load_addr__;
.noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){
. = ALIGN(8);
__noncacheable_init_start__ = .;
KEEP(*(.noncacheable.init))
__noncacheable_init_end__ = .;
KEEP(*(.noncacheable))
__noncacheable_bss_start__ = .;
KEEP(*(.noncacheable.bss))
__noncacheable_bss_end__ = .;
. = ALIGN(8);
} > SDRAM_NONCACHEABLE
.bss : {
. = ALIGN(8);
__bss_start__ = .;
*(.bss)
*(.bss*)
*(.tbss*)
*(.sbss*)
*(.scommon)
*(.scommon*)
*(.tcommon*)
*(.dynsbss*)
*(COMMON)
. = ALIGN(8);
_end = .;
__bss_end__ = .;
} > AXI_SRAM
.heap : {
. = ALIGN(8);
__heap_start__ = .;
. += HEAP_SIZE;
__heap_end__ = .;
} > SDRAM
.framebuffer (NOLOAD) : {
. = ALIGN(8);
KEEP(*(.framebuffer))
. = ALIGN(8);
} > SDRAM
.stack : {
. = ALIGN(8);
__stack_base__ = .;
. += STACK_SIZE;
. = ALIGN(8);
PROVIDE (_stack = .);
[libcpu][riscv]整合libcpu/riscv中的移植文件 提供一份公共代码于common (#6941) 整合libcpu/riscv中的移植文件 提供一份公共代码于common 在提交本pr时,除hpmicro的内核,rv32内核bsp已完成去除大部分的冗余,大部分代码采用common中的实现。本pr的作用是进一步统一common中的文件,从而提供一份公用代码,新移植的RV32内核的BSP可以全部使用common代码。 - 在common中提供一份公用文件:interrupt_gcc.S - 修改原有的文件,将原有的中断中上下文切换代码替换为interrupt_gcc.S - 基于上述修改,修改仓库中risc-v内核的BSP与移植相关的部分 (主要包含中断入口函数 中断栈等) - 在common中提供一份公用文件:trap_common.c;提供统一中断入口函数,中断入口函数初始化,中断入口注册等函数,并完善异常时的信息输出 - 在common中提供一份公用文件:rt_hw_stack_frame.h;将栈帧结构体剥离,供用户使用 - 在上述工作完成后,在上述工作的基础上测试仓库中risc-v内核的BSP - 完善函数中的命名,完善中断栈的获取 - 提供一份详细的基于现有common文件的移植指南 #### 在什么测试环境下测试通过 - 1.CH32V307V-R1-R0 - 2.CH32V208W-R0-1V4 - 3.HPM6750EVKMINI - 4.GD32VF103V-EVAL - 5.qemu(CORE-V-MCU ) > 与上述开发板使用同样芯片的BSP均测试通过 在CH32V307V-R1-R0与HPM6750EVKMINI上基于现有移植文件进行多线程复杂场景下的长时间测试,测试过程系统运行正常。
2023-03-01 14:32:43 +08:00
PROVIDE( __rt_rvstack = . );
PROVIDE (_stack_in_dlm = .);
} > AXI_SRAM
__noncacheable_start__ = ORIGIN(SDRAM_NONCACHEABLE);
__noncacheable_end__ = ORIGIN(SDRAM_NONCACHEABLE) + LENGTH(SDRAM_NONCACHEABLE);
}