2023-01-07 15:03:21 +08:00
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/****************************************************************************************
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* @file flash.ld
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*
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* @brief This file is the link script file (gnuarm or armgcc).
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*
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* Copyright (C) BouffaloLab 2021
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*
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****************************************************************************************
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*/
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/* configure the CPU type */
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OUTPUT_ARCH( "riscv" )
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/* link with the standard c library */
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INPUT(-lc)
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/* link with the standard GCC library */
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INPUT(-lgcc)
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/* configure the entry point */
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2023-03-19 14:41:18 +08:00
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ENTRY(__start)
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2023-01-07 15:03:21 +08:00
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2023-03-19 14:41:18 +08:00
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StackSize = 0x1000; /* 4KB */
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2023-01-07 15:03:21 +08:00
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HeapMinSize = 0x1000; /* 4KB */
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2023-03-19 14:41:18 +08:00
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__EM_SIZE = DEFINED(btble_controller_init) ? 32K : 0K;
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__RFTLV_SIZE_OFFSET = 1K;
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__RFTLV_SIZE_HOLE = 2K;
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__RFTLV_HEAD1_H = (0x46524C42); /* BLRF */
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__RFTLV_HEAD1_L = (0x41524150); /* PAPA */
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2023-01-07 15:03:21 +08:00
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MEMORY
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{
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2023-03-19 14:41:18 +08:00
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fw_header_memory (rx) : ORIGIN = 0xA0000000 - 0x1000, LENGTH = 4K
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xip_memory (rx) : ORIGIN = 0xA0000000, LENGTH = 4M
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ram_code (wxa) : ORIGIN = 0xA8000000, LENGTH = 4M
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itcm_memory (rx) : ORIGIN = 0x62FC0000, LENGTH = 20K
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dtcm_memory (rx) : ORIGIN = 0x62FC5000, LENGTH = 4K
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nocache_ram_memory (!rx) : ORIGIN = 0x22FC6000, LENGTH = 44K+60K
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ram_memory (!rx) : ORIGIN = 0x62FE0000, LENGTH = 320K-20K-4K-44K-60K
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ram_wifi (wxa) : ORIGIN = 0x23010000, LENGTH = 160K - __EM_SIZE
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2023-01-07 15:03:21 +08:00
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}
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SECTIONS
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{
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2023-03-19 14:41:18 +08:00
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BOOT2_PT_ADDR = 0x63027c00;
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.fw_header :
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{
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KEEP(*(.fw_header))
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} > fw_header_memory
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.init :
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{
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KEEP (*(SORT_NONE(.init)))
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KEEP (*(SORT_NONE(.vector)))
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} > xip_memory
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.rftlv.tool :
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{
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. = ORIGIN(xip_memory) + __RFTLV_SIZE_OFFSET;
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PROVIDE( _ld_symbol_rftlv_address = . );
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LONG(__RFTLV_HEAD1_H);
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LONG(__RFTLV_HEAD1_L);
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. = ORIGIN(xip_memory) + __RFTLV_SIZE_OFFSET + __RFTLV_SIZE_HOLE;
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} > xip_memory
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2023-01-07 15:03:21 +08:00
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.text :
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{
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. = ALIGN(4);
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__text_code_start__ = .;
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*(.text)
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*(.text.*)
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2023-03-19 14:41:18 +08:00
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/* section information for finsh shell */
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. = ALIGN(4);
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2023-01-07 15:03:21 +08:00
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__fsymtab_start = .;
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KEEP(*(FSymTab))
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__fsymtab_end = .;
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. = ALIGN(4);
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__vsymtab_start = .;
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KEEP(*(VSymTab))
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__vsymtab_end = .;
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2023-03-19 14:41:18 +08:00
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. = ALIGN(4);
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/* section information for modules */
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. = ALIGN(4);
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__rtmsymtab_start = .;
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KEEP(*(RTMSymTab))
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__rtmsymtab_end = .;
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/* section information for initialization */
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. = ALIGN(4);
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__rt_init_start = .;
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KEEP(*(SORT(.rti_fn*)))
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__rt_init_end = .;
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2023-01-07 15:03:21 +08:00
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2023-03-19 14:41:18 +08:00
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/* section information for usb usbh_class_info */
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2023-01-07 15:03:21 +08:00
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. = ALIGN(4);
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2023-03-19 14:41:18 +08:00
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__usbh_class_info_start__ = .;
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KEEP(*(.usbh_class_info))
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2023-01-07 15:03:21 +08:00
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. = ALIGN(4);
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2023-03-19 14:41:18 +08:00
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__usbh_class_info_end__ = .;
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2023-01-07 15:03:21 +08:00
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/*put .rodata**/
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2023-03-19 14:41:18 +08:00
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*(EXCLUDE_FILE( *bl616_glb*.o* \
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*bl616_pds*.o* \
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*bl616_common*.o* \
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*bl616_sf_cfg*.o* \
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*bl616_sf_ctrl*.o* \
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*bl616_sflash*.o* \
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*bl616_xip_sflash*.o* \
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*bl616_ef_ctrl*.o* \
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*bl616_romapi_patch*.o* ).rodata*)
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2023-01-07 15:03:21 +08:00
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*(.srodata)
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*(.srodata.*)
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. = ALIGN(4);
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__text_code_end__ = .;
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} > xip_memory
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. = ALIGN(4);
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__itcm_load_addr = .;
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.itcm_region : AT (__itcm_load_addr)
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{
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. = ALIGN(4);
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__tcm_code_start__ = .;
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*(.tcm_code.*)
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*(.tcm_const.*)
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*(.sclock_rlt_code.*)
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*(.sclock_rlt_const.*)
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2023-03-19 14:41:18 +08:00
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*bl616_glb*.o*(.rodata*)
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*bl616_pds*.o*(.rodata*)
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*bl616_common*.o*(.rodata*)
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*bl616_sf_cfg*.o*(.rodata*)
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*bl616_sf_ctrl*.o*(.rodata*)
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*bl616_sflash*.o*(.rodata*)
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*bl616_xip_sflash*.o*(.rodata*)
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*bl616_ef_ctrl*.o*(.rodata*)
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*bl616_romapi_patch*.o*(.rodata*)
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2023-01-07 15:03:21 +08:00
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. = ALIGN(4);
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__tcm_code_end__ = .;
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} > itcm_memory
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__dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
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.dtcm_region : AT (__dtcm_load_addr)
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{
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. = ALIGN(4);
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__tcm_data_start__ = .;
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*(.tcm_data)
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/* *finger_print.o(.data*) */
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. = ALIGN(4);
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__tcm_data_end__ = .;
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} > dtcm_memory
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/*************************************************************************/
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/* .stack_dummy section doesn't contains any symbols. It is only
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* used for linker to calculate size of stack sections, and assign
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* values to stack symbols later */
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.stack_dummy (NOLOAD):
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{
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. = ALIGN(0x4);
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. = . + StackSize;
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. = ALIGN(0x4);
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} > dtcm_memory
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/* Set stack top to end of RAM, and stack limit move down by
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* size of stack_dummy section */
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__StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
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PROVIDE( __freertos_irq_stack_top = __StackTop);
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PROVIDE( __rt_rvstack = . );
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__StackLimit = __StackTop - SIZEOF(.stack_dummy);
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/* Check if data + heap + stack exceeds RAM limit */
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ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
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2023-01-07 15:03:21 +08:00
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/*************************************************************************/
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2023-03-19 14:41:18 +08:00
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2023-01-07 15:03:21 +08:00
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__nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
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2023-03-19 14:41:18 +08:00
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.nocache_ram_region : AT (__nocache_ram_load_addr)
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2023-01-07 15:03:21 +08:00
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{
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. = ALIGN(4);
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__nocache_ram_data_start__ = .;
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*(.nocache_ram)
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. = ALIGN(4);
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__nocache_ram_data_end__ = .;
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} > nocache_ram_memory
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2023-03-19 14:41:18 +08:00
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__ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
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2023-01-07 15:03:21 +08:00
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/* Data section */
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RAM_DATA : AT (__ram_load_addr)
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{
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. = ALIGN(4);
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__ram_data_start__ = .;
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PROVIDE( __global_pointer$ = . + 0x800 );
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*(.data)
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*(.data.*)
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*(.sdata)
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*(.sdata.*)
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*(.sdata2)
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*(.sdata2.*)
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. = ALIGN(4);
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2023-03-19 14:41:18 +08:00
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__bflog_tags_start__ = .;
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*(.bflog_tags_array)
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. = ALIGN(4);
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__bflog_tags_end__ = .;
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2023-01-07 15:03:21 +08:00
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__ram_data_end__ = .;
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} > ram_memory
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__etext_final = (__ram_load_addr + SIZEOF (RAM_DATA));
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ASSERT(__etext_final <= ORIGIN(xip_memory) + LENGTH(xip_memory), "code memory overflow")
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.bss (NOLOAD) :
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{
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. = ALIGN(4);
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__bss_start__ = .;
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*(.bss*)
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*(.sbss*)
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*(COMMON)
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. = ALIGN(4);
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__bss_end__ = .;
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} > ram_memory
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.noinit_data (NOLOAD) :
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{
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. = ALIGN(4);
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__noinit_data_start__ = .;
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*(.noinit_data*)
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. = ALIGN(4);
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__noinit_data_end__ = .;
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} > ram_memory
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.nocache_noinit_ram_region (NOLOAD) :
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{
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. = ALIGN(4);
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2023-03-19 14:41:18 +08:00
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__nocache_noinit_ram_data_start__ = .;
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2023-01-07 15:03:21 +08:00
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*(.nocache_noinit_ram)
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2023-03-19 14:41:18 +08:00
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*(.noncacheable)
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2023-01-07 15:03:21 +08:00
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. = ALIGN(4);
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2023-03-19 14:41:18 +08:00
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__nocache_noinit_ram_data_end__ = .;
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2023-01-07 15:03:21 +08:00
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} > nocache_ram_memory
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.heap (NOLOAD):
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{
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. = ALIGN(4);
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__HeapBase = .;
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/*__end__ = .;*/
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/*end = __end__;*/
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KEEP(*(.heap*))
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. = ALIGN(4);
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__HeapLimit = .;
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} > ram_memory
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__HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
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ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow")
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2023-03-19 14:41:18 +08:00
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.psmram_data (NOLOAD):
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{
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. = ALIGN(4);
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__psram_data_start__ = .;
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/*__end__ = .;*/
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/*end = __end__;*/
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KEEP(*(.psram_data*))
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KEEP(*(.img_buf*))
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. = ALIGN(4);
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__psram_data_end__ = .;
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} > ram_code
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.wifibss (NOLOAD) :
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{
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PROVIDE( __wifi_bss_start = ADDR(.wifibss) );
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PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );
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_sshram = . ;
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*(SHAREDRAMIPC)
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*(SHAREDRAM)
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_eshram = . ;
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*ipc_shared.o(COMMON)
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*sdu_shared.o(COMMON)
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*hal_desc.o(COMMON)
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*txl_buffer_shared.o(COMMON)
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*txl_frame_shared.o(COMMON)
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*scan_shared.o(COMMON)
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*scanu_shared.o(COMMON)
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*mfp_bip.o(COMMON)
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*me_mic.o(COMMON)
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*(.wifi_ram*)
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. = ALIGN(16);
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} > ram_wifi
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PROVIDE( _heap_wifi_start = . );
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PROVIDE( _heap_wifi_size = ORIGIN(ram_wifi) + LENGTH(ram_wifi) - _heap_wifi_start );
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2023-01-07 15:03:21 +08:00
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}
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