103 lines
3.2 KiB
ArmAsm
103 lines
3.2 KiB
ArmAsm
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/*
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* File : mips_excpt_asm.S
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2016<EFBFBD><EFBFBD>9<EFBFBD><EFBFBD>7<EFBFBD><EFBFBD> Urey the first version
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*/
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#ifndef __ASSEMBLY__
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# define __ASSEMBLY__
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#endif
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#include "../common/mips.h"
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#define _EXC_STKSIZE 20*1024
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;/*********************************************************************************************************
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; PTE BASE <20><><EFBFBD>ض<EFBFBD><D8B6><EFBFBD>
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;*********************************************************************************************************/
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#define PTE_BASE_OFFSET 23
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#define PTE_BASE_SIZE 9
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#define MIPS32_BADVPN2_SHIFT 2
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.section ".text", "ax"
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.set noreorder
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LEAF(mips_tlb_refill_handlerx)
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.set push
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.set noat
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.set noreorder
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.set volatile
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;/*
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; * K1 = CP0_CTXT
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; * K0 = K1
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; */
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mfc0 k1 , CP0_CONTEXT ;/* K1 <20><><EFBFBD><EFBFBD> Context <20>Ĵ<EFBFBD><C4B4><EFBFBD> */
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ehb
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move k0 , k1 ;/* K0 <20><><EFBFBD><EFBFBD> Context <20>Ĵ<EFBFBD><C4B4><EFBFBD> */
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;/*
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; * K1 <<= PTE_BASE_SIZE
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; * K1 >>= PTE_BASE_SIZE
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; * K1 >>= 4
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; * K1 >>= MIPS32_BADVPN2_SHIFT
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; * K1 <<= 3
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; */
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sll k1 , PTE_BASE_SIZE
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srl k1 , (PTE_BASE_SIZE + 4 + MIPS32_BADVPN2_SHIFT) ;/* K1 Ϊ BAD VPN2 */
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sll k1 , (4 - 1)
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;/*
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; * K0 >>= PTE_BASE_OFFSET
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; * K0 <<= PTE_BASE_OFFSET
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; */
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srl k0 , PTE_BASE_OFFSET
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sll k0 , PTE_BASE_OFFSET ;/* K0 Ϊ PTE BASE */
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;/*
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; * K1 = K1 | K0
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; */
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or k1 , k1 , k0 ;/* <20>ϳ<EFBFBD> */
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;/*
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; * K0 = *K1
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; * K1 = *(K1 + 4)
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; */
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lw k0 , 0(k1)
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lw k1 , 4(k1)
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;/*
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; * CP0_TLBLO0 = K0
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; * CP0_TLBLO1 = K1
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; */
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mtc0 k0 , CP0_ENTRYLO0 ;/* EntryLo0 */
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mtc0 k1 , CP0_ENTRYLO1 ;/* EntryLo1 */
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ehb
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tlbwr ;/* TLB <20><><EFBFBD><EFBFBD><EFBFBD>滻 */
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eret ;/* <20>쳣<EFBFBD><ECB3A3><EFBFBD><EFBFBD> */
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.set pop
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END(mips_tlb_refill_handlerx)
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