2020-12-11 00:45:58 +08:00
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/*
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2021-09-22 09:29:19 +08:00
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* Copyright (c) 2006-2021, RT-Thread Development Team
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2020-12-11 00:45:58 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-10-28 0xcccccccccccc Initial Version
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*/
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/**
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* @addtogroup ls2k
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*/
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/*@{*/
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2020-12-08 10:13:52 +08:00
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#ifndef LS2K_DRV_SPI_H
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#define LS2K_DRV_SPI_H
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2020-11-30 14:57:21 +08:00
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2020-12-08 10:13:52 +08:00
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// kseg1 byte operation
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2021-09-22 09:29:19 +08:00
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#define KSEG1_STORE8(addr,val) *(volatile char *)(0xffffffffa0000000 | addr) = val
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#define KSEG1_LOAD8(addr) *(volatile char *)(0xffffffffa0000000 | addr)
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2020-12-08 10:13:52 +08:00
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// clock configurations
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2020-11-30 14:57:21 +08:00
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#define APB_MAX_SPEED 125000000U
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#define APB_FREQSCALE (((KSEG1_LOAD8(0xffffffffbfe104d2)>>4)&0x7)+1)
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2020-12-08 10:13:52 +08:00
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// base addrs
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2020-11-30 14:57:21 +08:00
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#define SPI_BASE 0x1fff0220
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#define PMON_ADDR 0xa1000000
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#define FLASH_ADDR 0x000000
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2020-12-08 10:13:52 +08:00
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// bit bias
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2020-11-30 14:57:21 +08:00
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#define SPCR 0x0
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#define SPSR 0x1
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2021-09-22 09:29:19 +08:00
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#define FIFO 0x2
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2020-11-30 14:57:21 +08:00
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#define TXFIFO 0x2
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#define RXFIFO 0x2
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#define SPER 0x3
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#define PARAM 0x4
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#define SOFTCS 0x5
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#define PARAM2 0x6
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2020-12-08 10:13:52 +08:00
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#define RFEMPTY 1
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// SPI controller operaion macros
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2020-11-30 14:57:21 +08:00
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#define SET_SPI(addr,val) KSEG1_STORE8(SPI_BASE+addr,val)
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#define GET_SPI(addr) KSEG1_LOAD8(SPI_BASE+addr)
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#endif
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2020-12-11 00:45:58 +08:00
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/*@}*/
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