398 lines
10 KiB
C
398 lines
10 KiB
C
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/**
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*****************************************************************************
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* @file cmem7_flash.c
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*
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* @brief CMEM7 flash controller source file
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*
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*
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* @version V1.0
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* @date 3. September 2013
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*
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* @note
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*
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*****************************************************************************
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* @attention
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2013 Capital-micro </center></h2>
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*****************************************************************************
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*/
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#include "cmem7_flash.h"
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typedef struct {
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union {
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uint16_t STATUS; /*!< status register */
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struct {
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uint16_t WIP: 1; /*!< in writting */
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uint16_t WEL: 1; /*!< write enable */
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uint16_t BP: 5; /*!< protection region */
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uint16_t SRP: 2; /*!< protection mode */
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uint16_t QE: 1; /*!< Quad mode */
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} STATUS_b; /*!< BitSize */
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} INNER;
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} FLASH_INNER_STATUS;
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#define NS_IN_A_SECOND (1000000000)
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#define FLASH_MAX_SIZE 0x800000
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#define FLASH_PAGE_SIZE 0x100
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#define FLASH_SECTOR_SIZE 0x001000
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#define FLASH_BLOCK_32K_SIZE 0x008000
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#define FLASH_BLOCK_64K_SIZE 0x010000
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#define FLASH_CMD_RD_INNER_STATUS_LOW 0x05
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#define FLASH_CMD_RD_INNER_STATUS_HIGH 0x35
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#define FLASH_CMD_WR_WRITE_ENABLE 0x06
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#define FLASH_CMD_WR_WRITE_DISABLE 0x04
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#define FLASH_CME_WR_STATUS_REG 0x01
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#define FLASH_CME_ERASE_SECTOR 0x20
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#define FLASH_CME_ERASE_BLOCK_32K 0x52
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#define FLASH_CME_ERASE_BLOCK_64K 0xD8
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#define FLASH_CME_ERASE_CHIP 0xC7
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#define FLASH_CME_WR_ENTER_DEEP_PD 0xB9
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#define FLASH_CME_WR_EXIT_DEEP_PD 0xAB
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#define FLASH_CME_RD_NORMAL 0x03
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#define FLASH_CME_RD_FAST 0x0B
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#define FLASH_CME_RD_FAST_DUAL 0x3B
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#define FLASH_CME_RD_FAST_QUAD 0x6B
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#define FLASH_CME_WR 0x02
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typedef void (*WAIT)(void);
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static WAIT wait;
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static void flash_setClock(uint8_t dividor) {
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dividor = (dividor < 2) ? 2 : dividor;
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NOR_FLASH->CTRL0_b.DIV = dividor / 2 - 1;
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}
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static void flash_cleanOperation() {
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NOR_FLASH->TRIGGER_b.OP_CLEAN = TRUE;
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while (NOR_FLASH->STATUS_b.BUSY);
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NOR_FLASH->TRIGGER_b.OP_CLEAN = FALSE;
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while (NOR_FLASH->STATUS_b.BUSY);
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}
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static uint8_t flash_ReadInnerStatusLow() {
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NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 1;
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NOR_FLASH->CTRL1_b.CMD = FLASH_CMD_RD_INNER_STATUS_LOW;
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NOR_FLASH->TRIGGER_b.OP_START = TRUE;
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while (NOR_FLASH->STATUS_b.BUSY);
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return (uint8_t)NOR_FLASH->DATA;
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}
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static uint8_t flash_ReadInnerStatusHigh() {
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NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 1;
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NOR_FLASH->CTRL1_b.CMD = FLASH_CMD_RD_INNER_STATUS_HIGH;
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NOR_FLASH->TRIGGER_b.OP_START = TRUE;
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while (NOR_FLASH->STATUS_b.BUSY);
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return (uint8_t)NOR_FLASH->DATA;
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}
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static void flash_WaitInWritting() {
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FLASH_INNER_STATUS s;
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while (NOR_FLASH->STATUS_b.BUSY);
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do {
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s.INNER.STATUS = flash_ReadInnerStatusLow();
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if (!s.INNER.STATUS_b.WIP) {
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break;
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}
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if (wait) {
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(*wait)();
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}
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} while (1);
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}
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static void flash_WriteWriteEnable(BOOL enable) {
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NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 0;
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NOR_FLASH->CTRL1_b.CMD =
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enable ? FLASH_CMD_WR_WRITE_ENABLE : FLASH_CMD_WR_WRITE_DISABLE;
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NOR_FLASH->TRIGGER_b.OP_START = TRUE;
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flash_WaitInWritting();
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}
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static void flash_WriteStatusReg(FLASH_INNER_STATUS *s) {
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uint16_t tmp = s->INNER.STATUS;
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NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 2;
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NOR_FLASH->CTRL1_b.CMD = FLASH_CME_WR_STATUS_REG;
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NOR_FLASH->DATA = ((tmp << 8) | (tmp >> 8)) << 16;
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NOR_FLASH->TRIGGER_b.OP_START = TRUE;
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flash_WaitInWritting();
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}
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static void flash_Erase(uint8_t cmd, uint32_t addr) {
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NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 0;
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NOR_FLASH->CTRL1_b.CMD = cmd;
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NOR_FLASH->CTRL1_b.ADDRESS = addr;
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NOR_FLASH->TRIGGER_b.OP_START = TRUE;
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flash_WaitInWritting();
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}
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static void flash_WriteDeepPowerDownEnable(BOOL enable) {
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NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 0;
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NOR_FLASH->CTRL1_b.CMD =
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enable ? FLASH_CME_WR_ENTER_DEEP_PD : FLASH_CME_WR_EXIT_DEEP_PD;
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NOR_FLASH->TRIGGER_b.OP_START = TRUE;
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flash_WaitInWritting();
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}
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static void flash_RwReq(uint8_t cmd, uint32_t addr, uint16_t size) {
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NOR_FLASH->CTRL0_b.RW_BYTE_CNT = size;
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NOR_FLASH->CTRL1_b.CMD = cmd;
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NOR_FLASH->CTRL1_b.ADDRESS = addr;
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NOR_FLASH->TRIGGER_b.OP_START = TRUE;
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}
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static void flash_WaitReadFifoNotEmpty() {
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while (NOR_FLASH->STATUS_b.RD_FIFO_EMPTY) {
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if (wait) {
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(*wait)();
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}
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}
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}
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static uint16_t flash_ReadFifo(uint16_t size, uint8_t* data) {
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uint16_t count = 0;
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while (!NOR_FLASH->STATUS_b.RD_FIFO_EMPTY && size != 0) {
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uint32_t d = NOR_FLASH->DATA;
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if (size > 3) {
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*(data + count++) = d >> 24;
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*(data + count++) = (d & 0x00FF0000) >> 16;
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*(data + count++) = (d & 0x0000FF00) >> 8;
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*(data + count++) = (d & 0x000000FF);
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size -= 4;
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} else if (size == 3) {
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*(data + count++) = (d & 0x00FF0000) >> 16;
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*(data + count++) = (d & 0x0000FF00) >> 8;
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*(data + count++) = (d & 0x000000FF);
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size -= 3;
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} else if (size == 2) {
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*(data + count++) = (d & 0x0000FF00) >> 8;
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*(data + count++) = (d & 0x000000FF);
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size -= 2;
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} else if (size == 1) {
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*(data + count++) = (d & 0x000000FF);
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size -= 1;
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}
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}
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return count;
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}
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static uint16_t flash_WriteFifo(uint16_t size, uint8_t* data) {
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uint16_t count = 0;
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while (!NOR_FLASH->STATUS_b.WR_FIFO_FULL && size != 0) {
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uint32_t d = 0;
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if (size > 3) {
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d = *(data + count++) << 24;
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d |= *(data + count++) << 16;
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d |= *(data + count++) << 8;
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d |= *(data + count++);
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size -= 4;
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} else if (size == 3) {
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d = *(data + count++) << 24;
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d |= *(data + count++) << 16;
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d |= *(data + count++) << 8;
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size -= 3;
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} else if (size == 2) {
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d = *(data + count++) << 24;
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d |= *(data + count++) << 16;
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size -= 2;
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} else if (size == 1) {
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d = *(data + count++) << 24;
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size -= 1;
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}
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NOR_FLASH->DATA = d;
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}
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return count;
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}
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static uint16_t flash_WritePage(uint32_t addr, uint16_t size, uint8_t* data) {
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uint16_t actualSize, retSize;
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flash_WriteWriteEnable(TRUE);
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actualSize = FLASH_PAGE_SIZE - (addr & (FLASH_PAGE_SIZE - 1));
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actualSize = (size > actualSize) ? actualSize : size;
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retSize = actualSize;
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flash_RwReq(FLASH_CME_WR, addr, actualSize);
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while (actualSize != 0) {
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uint8_t count = flash_WriteFifo(actualSize, data);
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actualSize -= count;
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data += count;
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}
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flash_WaitInWritting();
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return retSize;
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}
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void FLASH_Init(FLASH_InitTypeDef* init) {
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FLASH_INNER_STATUS s;
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assert_param(init);
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assert_param(IS_FLASH_PROTECT_MODE(init->FLASH_ProtectMode));
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assert_param(IS_FLASH_PROTECT_REGION(init->FLASH_ProtectRegion));
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wait = init->FLASH_Wait;
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flash_setClock(init->FLASH_ClockDividor);
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flash_cleanOperation();
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flash_WaitInWritting();
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s.INNER.STATUS = flash_ReadInnerStatusLow();
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s.INNER.STATUS |= ((uint16_t)flash_ReadInnerStatusHigh()) << 8;
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s.INNER.STATUS_b.BP = init->FLASH_ProtectRegion;
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s.INNER.STATUS_b.SRP = init->FLASH_ProtectMode;
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s.INNER.STATUS_b.QE = init->FLASH_QuadEnable;
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flash_WriteWriteEnable(TRUE);
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flash_WriteStatusReg(&s);
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}
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void FLASH_GetStatus(uint8_t* ProtectMode, uint8_t* ProtectRegion, BOOL* QuadEnable) {
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FLASH_INNER_STATUS s;
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assert_param(ProtectMode);
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assert_param(ProtectRegion);
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assert_param(QuadEnable);
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flash_WaitInWritting();
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s.INNER.STATUS = flash_ReadInnerStatusLow();
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s.INNER.STATUS |= ((uint16_t)flash_ReadInnerStatusHigh()) << 8;
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*ProtectRegion = s.INNER.STATUS_b.BP;
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*ProtectMode = s.INNER.STATUS_b.SRP;
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*QuadEnable = (s.INNER.STATUS_b.QE == 1) ? TRUE : FALSE;
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}
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void FLASH_EraseSector(uint32_t addr) {
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flash_WaitInWritting();
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flash_WriteWriteEnable(TRUE);
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addr = (addr << 8) >> 8;
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addr = addr / FLASH_SECTOR_SIZE * FLASH_SECTOR_SIZE;
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flash_Erase(FLASH_CME_ERASE_SECTOR, addr);
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}
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void FLASH_Erase32kBlock(uint32_t addr) {
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flash_WaitInWritting();
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flash_WriteWriteEnable(TRUE);
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addr = (addr << 8) >> 8;
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addr = addr / FLASH_BLOCK_32K_SIZE * FLASH_BLOCK_32K_SIZE;
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flash_Erase(FLASH_CME_ERASE_BLOCK_32K, addr);
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}
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void FLASH_Erase64kBlock(uint32_t addr) {
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flash_WaitInWritting();
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flash_WriteWriteEnable(TRUE);
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addr = (addr << 8) >> 8;
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addr = addr / FLASH_BLOCK_64K_SIZE * FLASH_BLOCK_64K_SIZE;
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flash_Erase(FLASH_CME_ERASE_BLOCK_64K, addr);
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}
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void FLASH_EraseChip(void) {
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flash_WaitInWritting();
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flash_WriteWriteEnable(TRUE);
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flash_Erase(FLASH_CME_ERASE_CHIP, 0x0);
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}
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void FLASH_EnableDeepPowerDown(BOOL enable) {
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flash_WaitInWritting();
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flash_WriteWriteEnable(TRUE);
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flash_WriteDeepPowerDownEnable(enable);
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}
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void FLASH_Read(uint8_t ReadMode, uint32_t addr, uint16_t size, uint8_t* data) {
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uint8_t cmd;
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assert_param(IS_FLASH_READ_MODE(ReadMode));
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assert_param(addr + size <= FLASH_MAX_SIZE);
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assert_param(data);
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if (size == 0) {
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return ;
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}
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flash_WaitInWritting();
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if (ReadMode == FLASH_READ_MODE_NORMAL) {
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cmd = FLASH_CME_RD_NORMAL;
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} else if (ReadMode == FLASH_READ_MODE_FAST) {
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cmd = FLASH_CME_RD_FAST;
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} else if (ReadMode == FLASH_READ_MODE_FAST_DUAL) {
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||
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|
cmd = FLASH_CME_RD_FAST_DUAL;
|
||
|
|
} else {
|
||
|
|
cmd = FLASH_CME_RD_FAST_QUAD;
|
||
|
|
}
|
||
|
|
|
||
|
|
flash_RwReq(cmd, addr, size);
|
||
|
|
|
||
|
|
while (size > 0) {
|
||
|
|
uint16_t count = 0;
|
||
|
|
|
||
|
|
flash_WaitReadFifoNotEmpty();
|
||
|
|
|
||
|
|
count = flash_ReadFifo(size, data);
|
||
|
|
size -= count;
|
||
|
|
data += count;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
void FLASH_Write(uint32_t addr, uint16_t size, uint8_t* data) {
|
||
|
|
assert_param(addr + size <= FLASH_MAX_SIZE);
|
||
|
|
assert_param(data);
|
||
|
|
|
||
|
|
flash_WaitInWritting();
|
||
|
|
|
||
|
|
while (size > 0) {
|
||
|
|
uint16_t count = flash_WritePage(addr, size, data);
|
||
|
|
|
||
|
|
addr += count;
|
||
|
|
size -= count;
|
||
|
|
data += count;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|