136 lines
5.5 KiB
C
136 lines
5.5 KiB
C
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/*
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* Copyright (C) 2011-2012, Freescale Semiconductor, Inc. All Rights Reserved
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* THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
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* BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
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* Freescale Semiconductor, Inc.
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*/
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#ifndef _GPIO_DEFINE_H_
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#define _GPIO_DEFINE_H_
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#if 0
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#define GPIO_DR_OFFSET 0x0000
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#define GPIO_GDIR_OFFSET 0x0004
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#define GPIO_PSR_OFFSET 0x0008
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#endif
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typedef enum {
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GPIO_PORT1 = 0,
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GPIO_PORT2 = 1,
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GPIO_PORT3 = 2,
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GPIO_PORT4 = 3,
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GPIO_PORT5 = 4,
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GPIO_PORT6 = 5,
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GPIO_PORT7 = 6,
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} GPIO_PORT;
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typedef struct {
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unsigned int DR;
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unsigned int GDIR;
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unsigned int PSR;
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unsigned int ICR1;
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unsigned int ICR2;
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unsigned int IMR;
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unsigned int ISR;
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unsigned int EDGE_SEL;
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} CSP_GPIO_REGS, *PCSP_GPIO_REGS;
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#define GPIO_GDIR_INPUT 0 // GPIO pin is input
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#define GPIO_GDIR_OUTPUT 1 // GPIO pin is output
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#define GPIO_LOW_LEVEL 0 // GPIO pin is low
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#define GPIO_HIGH_LEVEL 1 // GPIO pin is high
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#define GPIO_ICR_LOW_LEVEL 0 // Interrupt is low-level
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#define GPIO_ICR_HIGH_LEVEL 1 // Interrupt is high-level
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#define GPIO_ICR_RISE_EDGE 2 // Interrupt is rising edge
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#define GPIO_ICR_FALL_EDGE 3 // Interrupt is falling edge
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#define GPIO_IMR_MASKED 0 // Interrupt is masked
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#define GPIO_IMR_UNMASKED 1 // Interrupt is unmasked
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#define GPIO_EDGE_SEL_DISABLE 0 // Edge select is disabled
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#define GPIO_EDGE_SEL_ENABLE 1 // Edge select is enabled
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#define GPIO_PIN_MASK(pin) (1U << (pin))
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#define GPIO_PIN_VAL(val, pin) ((val) << (pin))
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#define GPIO_ICR_MASK(pin) (0x3U << ((pin) << 1))
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#define GPIO_ICR_VAL(val, pin) ((val) << ((pin) << 1))
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//#########################################
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//# GPIO peripheral defines
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//#########################################
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#define GPIO_DR0_OFFSET 0x00 // 32bit gpio pta data direction reg
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#define GPIO_GDIR0_OFFSET 0x04 // 32bit gpio pta output config 1 reg
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#define GPIO_PSR0_OFFSET 0x08 // 32bit gpio pta output config 2 reg
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#define GPIO_ICR1_OFFSET 0x0C // 32bit gpio pta input config A1 reg
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#define GPIO_ICR2_OFFSET 0x10 // 32bit gpio pta input config A2 reg
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#define GPIO_IMR_OFFSET 0x14 // 32bit gpio pta input config B1 reg
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#define GPIO_ISR_OFFSET 0x18 // GPIO Interrupt Status Register
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#define GPIO_EDGE_SEL_OFFSET 0x1C // GPIO Edge Detect Register
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#define GPIO1_DR GPIO1_BASE_ADDR+0x00
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#define GPIO1_GDIR GPIO1_BASE_ADDR+0x04
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#define GPIO1_PSR GPIO1_BASE_ADDR+0x08
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#define GPIO1_ICR1 GPIO1_BASE_ADDR+0x0C
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#define GPIO1_ICR2 GPIO1_BASE_ADDR+0x10
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#define GPIO1_IMR GPIO1_BASE_ADDR+0x14
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#define GPIO1_ISR GPIO1_BASE_ADDR+0x18
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#define GPIO1_EDGE_SEL GPIO1_BASE_ADDR+0x1C
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#define GPIO2_DR GPIO2_BASE_ADDR+0x00
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#define GPIO2_GDIR GPIO2_BASE_ADDR+0x04
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#define GPIO2_PSR GPIO2_BASE_ADDR+0x08
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#define GPIO2_ICR1 GPIO2_BASE_ADDR+0x0C
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#define GPIO2_ICR2 GPIO2_BASE_ADDR+0x10
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#define GPIO2_IMR GPIO2_BASE_ADDR+0x14
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#define GPIO2_ISR GPIO2_BASE_ADDR+0x18
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#define GPIO2_EDGE_SEL GPIO2_BASE_ADDR+0x1C
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#define GPIO3_DR GPIO3_BASE_ADDR+0x00
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#define GPIO3_GDIR GPIO3_BASE_ADDR+0x04
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#define GPIO3_PSR GPIO3_BASE_ADDR+0x08
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#define GPIO3_ICR1 GPIO3_BASE_ADDR+0x0C
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#define GPIO3_ICR2 GPIO3_BASE_ADDR+0x10
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#define GPIO3_IMR GPIO3_BASE_ADDR+0x14
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#define GPIO3_ISR GPIO3_BASE_ADDR+0x18
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#define GPIO3_EDGE_SEL GPIO3_BASE_ADDR+0x1C
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#define GPIO4_DR GPIO4_BASE_ADDR+0x00
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#define GPIO4_GDIR GPIO4_BASE_ADDR+0x04
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#define GPIO4_PSR GPIO4_BASE_ADDR+0x08
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#define GPIO4_ICR1 GPIO4_BASE_ADDR+0x0C
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#define GPIO4_ICR2 GPIO4_BASE_ADDR+0x10
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#define GPIO4_IMR GPIO4_BASE_ADDR+0x14
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#define GPIO4_ISR GPIO4_BASE_ADDR+0x18
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#define GPIO4_EDGE_SEL GPIO4_BASE_ADDR+0x1C
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#define GPIO5_DR GPIO5_BASE_ADDR+0x00
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#define GPIO5_GDIR GPIO5_BASE_ADDR+0x04
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#define GPIO5_PSR GPIO5_BASE_ADDR+0x08
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#define GPIO5_ICR1 GPIO5_BASE_ADDR+0x0C
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#define GPIO5_ICR2 GPIO5_BASE_ADDR+0x10
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#define GPIO5_IMR GPIO5_BASE_ADDR+0x14
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#define GPIO5_ISR GPIO5_BASE_ADDR+0x18
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#define GPIO5_EDGE_SEL GPIO5_BASE_ADDR+0x1C
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#define GPIO6_DR GPIO6_BASE_ADDR+0x00
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#define GPIO6_GDIR GPIO6_BASE_ADDR+0x04
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#define GPIO6_PSR GPIO6_BASE_ADDR+0x08
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#define GPIO6_ICR1 GPIO6_BASE_ADDR+0x0C
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#define GPIO6_ICR2 GPIO6_BASE_ADDR+0x10
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#define GPIO6_IMR GPIO6_BASE_ADDR+0x14
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#define GPIO6_ISR GPIO6_BASE_ADDR+0x18
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#define GPIO6_EDGE_SEL GPIO6_BASE_ADDR+0x1C
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#define GPIO7_DR GPIO7_BASE_ADDR+0x00
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#define GPIO7_GDIR GPIO7_BASE_ADDR+0x04
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#define GPIO7_PSR GPIO7_BASE_ADDR+0x08
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#define GPIO7_ICR1 GPIO7_BASE_ADDR+0x0C
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#define GPIO7_ICR2 GPIO7_BASE_ADDR+0x10
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#define GPIO7_IMR GPIO7_BASE_ADDR+0x14
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#define GPIO7_ISR GPIO7_BASE_ADDR+0x18
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#define GPIO7_EDGE_SEL GPIO7_BASE_ADDR+0x1C
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#endif
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