2020-03-14 17:50:53 +08:00
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/*
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2021-03-14 15:33:55 +08:00
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* Copyright (c) 2006-2021, RT-Thread Development Team
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2020-03-14 17:50:53 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-11-5 SummerGift first version
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*/
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#ifndef __BOARD_H__
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#define __BOARD_H__
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#include <rtthread.h>
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#include <stm32l4xx.h>
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#include "drv_common.h"
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#include "drv_gpio.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
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#define STM32_FLASH_SIZE (1024 * 1024)
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#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
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#define STM32_SRAM1_SIZE (256)
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#define STM32_SRAM1_START (0x20000000)
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#define STM32_SRAM1_END (STM32_SRAM1_START + STM32_SRAM1_SIZE * 1024)
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#if defined(__CC_ARM) || defined(__CLANG_ARM)
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extern int Image$$RW_IRAM1$$ZI$$Limit;
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#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
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#elif __ICCARM__
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#pragma section="CSTACK"
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#define HEAP_BEGIN (__segment_end("CSTACK"))
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#else
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extern int __bss_end;
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#define HEAP_BEGIN ((void *)&__bss_end)
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#endif
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#define HEAP_END STM32_SRAM1_END
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void SystemClock_Config(void);
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void SystemClock_MSI_ON(void);
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void SystemClock_MSI_OFF(void);
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void SystemClock_80M(void);
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void SystemClock_24M(void);
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void SystemClock_2M(void);
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void SystemClock_ReConfig(uint8_t mode);
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#ifdef __cplusplus
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}
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#endif
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#endif
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