54 lines
1.2 KiB
C
54 lines
1.2 KiB
C
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/*
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* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-04-28 CDT first version
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*/
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#ifndef __BOARD_H__
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#define __BOARD_H__
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#include <rtthread.h>
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#include "hc32_ll.h"
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#include "drv_gpio.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define HC32_FLASH_SIZE_GRANULARITY (8 * 1024)
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#define HC32_FLASH_SIZE (2 * 1024 * 1024)
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#define HC32_FLASH_START_ADDRESS (0)
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#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
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#define HC32_SRAM_SIZE (512)
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#define HC32_SRAM_END (0x1FFE0000 + HC32_SRAM_SIZE * 1024)
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#ifdef __ARMCC_VERSION
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extern int Image$$RW_IRAM2$$ZI$$Limit;
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#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit)
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#elif __ICCARM__
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#pragma section="HEAP"
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#define HEAP_BEGIN (__segment_end("HEAP"))
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#else
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extern int __bss_end;
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#define HEAP_BEGIN (&__bss_end)
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#endif
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#define HEAP_END HC32_SRAM_END
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void PeripheralRegister_Unlock(void);
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void PeripheralClock_Config(void);
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void SystemBase_Config(void);
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void SystemClock_Config(void);
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#ifdef __cplusplus
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}
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#endif
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#endif
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