321 lines
10 KiB
C
321 lines
10 KiB
C
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/*
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* The Clear BSD License
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_flexio.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.flexio"
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#endif
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/*< @brief user configurable flexio handle count. */
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#define FLEXIO_HANDLE_COUNT 2
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Pointers to flexio bases for each instance. */
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FLEXIO_Type *const s_flexioBases[] = FLEXIO_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to flexio clocks for each instance. */
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const clock_ip_name_t s_flexioClocks[] = FLEXIO_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*< @brief pointer to array of FLEXIO handle. */
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static void *s_flexioHandle[FLEXIO_HANDLE_COUNT];
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/*< @brief pointer to array of FLEXIO IP types. */
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static void *s_flexioType[FLEXIO_HANDLE_COUNT];
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/*< @brief pointer to array of FLEXIO Isr. */
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static flexio_isr_t s_flexioIsr[FLEXIO_HANDLE_COUNT];
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/*******************************************************************************
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* Codes
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******************************************************************************/
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uint32_t FLEXIO_GetInstance(FLEXIO_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_flexioBases); instance++)
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{
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if (s_flexioBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_flexioBases));
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return instance;
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}
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void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig)
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{
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uint32_t ctrlReg = 0;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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CLOCK_EnableClock(s_flexioClocks[FLEXIO_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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FLEXIO_Reset(base);
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ctrlReg = base->CTRL;
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ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK);
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ctrlReg |= (FLEXIO_CTRL_DBGE(userConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(userConfig->enableFastAccess) |
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FLEXIO_CTRL_FLEXEN(userConfig->enableFlexio));
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if (!userConfig->enableInDoze)
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{
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ctrlReg |= FLEXIO_CTRL_DOZEN_MASK;
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}
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base->CTRL = ctrlReg;
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}
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void FLEXIO_Deinit(FLEXIO_Type *base)
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{
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FLEXIO_Enable(base, false);
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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CLOCK_DisableClock(s_flexioClocks[FLEXIO_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig)
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{
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assert(userConfig);
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userConfig->enableFlexio = true;
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userConfig->enableInDoze = false;
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userConfig->enableInDebug = true;
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userConfig->enableFastAccess = false;
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}
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void FLEXIO_Reset(FLEXIO_Type *base)
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{
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/*do software reset, software reset operation affect all other FLEXIO registers except CTRL*/
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base->CTRL |= FLEXIO_CTRL_SWRST_MASK;
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base->CTRL = 0;
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}
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uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index)
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{
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assert(index < FLEXIO_SHIFTBUF_COUNT);
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uint32_t address = 0;
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switch (type)
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{
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case kFLEXIO_ShifterBuffer:
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address = (uint32_t) & (base->SHIFTBUF[index]);
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break;
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case kFLEXIO_ShifterBufferBitSwapped:
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address = (uint32_t) & (base->SHIFTBUFBIS[index]);
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break;
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case kFLEXIO_ShifterBufferByteSwapped:
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address = (uint32_t) & (base->SHIFTBUFBYS[index]);
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break;
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case kFLEXIO_ShifterBufferBitByteSwapped:
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address = (uint32_t) & (base->SHIFTBUFBBS[index]);
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break;
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#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP
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case kFLEXIO_ShifterBufferNibbleByteSwapped:
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address = (uint32_t) & (base->SHIFTBUFNBS[index]);
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break;
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#endif
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#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP
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case kFLEXIO_ShifterBufferHalfWordSwapped:
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address = (uint32_t) & (base->SHIFTBUFHWS[index]);
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break;
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#endif
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#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP
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case kFLEXIO_ShifterBufferNibbleSwapped:
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address = (uint32_t) & (base->SHIFTBUFNIS[index]);
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break;
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#endif
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default:
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break;
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}
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return address;
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}
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void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig)
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{
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base->SHIFTCFG[index] = FLEXIO_SHIFTCFG_INSRC(shifterConfig->inputSource)
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#if FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH
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| FLEXIO_SHIFTCFG_PWIDTH(shifterConfig->parallelWidth)
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#endif /* FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH */
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| FLEXIO_SHIFTCFG_SSTOP(shifterConfig->shifterStop) |
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FLEXIO_SHIFTCFG_SSTART(shifterConfig->shifterStart);
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base->SHIFTCTL[index] =
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FLEXIO_SHIFTCTL_TIMSEL(shifterConfig->timerSelect) | FLEXIO_SHIFTCTL_TIMPOL(shifterConfig->timerPolarity) |
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FLEXIO_SHIFTCTL_PINCFG(shifterConfig->pinConfig) | FLEXIO_SHIFTCTL_PINSEL(shifterConfig->pinSelect) |
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FLEXIO_SHIFTCTL_PINPOL(shifterConfig->pinPolarity) | FLEXIO_SHIFTCTL_SMOD(shifterConfig->shifterMode);
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}
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void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig)
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{
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base->TIMCFG[index] =
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FLEXIO_TIMCFG_TIMOUT(timerConfig->timerOutput) | FLEXIO_TIMCFG_TIMDEC(timerConfig->timerDecrement) |
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FLEXIO_TIMCFG_TIMRST(timerConfig->timerReset) | FLEXIO_TIMCFG_TIMDIS(timerConfig->timerDisable) |
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FLEXIO_TIMCFG_TIMENA(timerConfig->timerEnable) | FLEXIO_TIMCFG_TSTOP(timerConfig->timerStop) |
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FLEXIO_TIMCFG_TSTART(timerConfig->timerStart);
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base->TIMCMP[index] = FLEXIO_TIMCMP_CMP(timerConfig->timerCompare);
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base->TIMCTL[index] = FLEXIO_TIMCTL_TRGSEL(timerConfig->triggerSelect) |
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FLEXIO_TIMCTL_TRGPOL(timerConfig->triggerPolarity) |
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FLEXIO_TIMCTL_TRGSRC(timerConfig->triggerSource) |
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FLEXIO_TIMCTL_PINCFG(timerConfig->pinConfig) | FLEXIO_TIMCTL_PINSEL(timerConfig->pinSelect) |
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FLEXIO_TIMCTL_PINPOL(timerConfig->pinPolarity) | FLEXIO_TIMCTL_TIMOD(timerConfig->timerMode);
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}
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status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr)
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{
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assert(base);
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assert(handle);
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assert(isr);
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uint8_t index = 0;
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/* Find the an empty handle pointer to store the handle. */
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for (index = 0; index < FLEXIO_HANDLE_COUNT; index++)
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{
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if (s_flexioHandle[index] == NULL)
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{
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/* Register FLEXIO simulated driver base, handle and isr. */
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s_flexioType[index] = base;
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s_flexioHandle[index] = handle;
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s_flexioIsr[index] = isr;
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break;
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}
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}
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if (index == FLEXIO_HANDLE_COUNT)
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{
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return kStatus_OutOfRange;
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}
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else
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{
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return kStatus_Success;
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}
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}
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status_t FLEXIO_UnregisterHandleIRQ(void *base)
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{
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assert(base);
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uint8_t index = 0;
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/* Find the index from base address mappings. */
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for (index = 0; index < FLEXIO_HANDLE_COUNT; index++)
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{
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if (s_flexioType[index] == base)
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{
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/* Unregister FLEXIO simulated driver handle and isr. */
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s_flexioType[index] = NULL;
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s_flexioHandle[index] = NULL;
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s_flexioIsr[index] = NULL;
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break;
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}
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}
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if (index == FLEXIO_HANDLE_COUNT)
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{
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return kStatus_OutOfRange;
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}
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else
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{
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return kStatus_Success;
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}
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}
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void FLEXIO_CommonIRQHandler(void)
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{
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uint8_t index;
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for (index = 0; index < FLEXIO_HANDLE_COUNT; index++)
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{
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if (s_flexioHandle[index])
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{
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s_flexioIsr[index](s_flexioType[index], s_flexioHandle[index]);
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}
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}
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/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
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exception return operation might vector to incorrect interrupt */
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#if defined __CORTEX_M && (__CORTEX_M == 4U)
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__DSB();
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#endif
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}
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void FLEXIO_DriverIRQHandler(void)
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{
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FLEXIO_CommonIRQHandler();
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}
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void FLEXIO0_DriverIRQHandler(void)
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{
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FLEXIO_CommonIRQHandler();
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}
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void FLEXIO1_DriverIRQHandler(void)
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{
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FLEXIO_CommonIRQHandler();
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}
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void UART2_FLEXIO_DriverIRQHandler(void)
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{
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FLEXIO_CommonIRQHandler();
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}
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void FLEXIO2_DriverIRQHandler(void)
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{
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FLEXIO_CommonIRQHandler();
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}
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