2022-04-05 19:34:30 +08:00
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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*/
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2013-01-08 22:40:58 +08:00
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#ifndef __RTTHREAD_CFG_H__
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#define __RTTHREAD_CFG_H__
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/* Includes ------------------------------------------------------------------*/
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/* Exported macro ------------------------------------------------------------*/
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2017-03-16 11:29:29 +08:00
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/* EFM32_BOARD */
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//#define EFM32_G8XX_STK
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//#define EFM32_GXXX_DK
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#define EFM32GG_DK3750
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/* RT_NAME_MAX */
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2021-03-27 15:16:57 +08:00
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#define RT_NAME_MAX (8)
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2013-01-08 22:40:58 +08:00
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2017-03-16 11:29:29 +08:00
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/* RT_ALIGN_SIZE */
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2021-03-27 15:16:57 +08:00
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#define RT_ALIGN_SIZE (4)
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2013-01-08 22:40:58 +08:00
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/* PRIORITY_MAX */
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2021-03-27 15:16:57 +08:00
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#define RT_THREAD_PRIORITY_MAX (32)
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2013-01-08 22:40:58 +08:00
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/* Tick per Second */
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2021-03-27 15:16:57 +08:00
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#define RT_TICK_PER_SECOND (100)
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2013-01-08 22:40:58 +08:00
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/* SECTION: RT_DEBUG */
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#define RT_DEBUG
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2019-03-06 17:07:15 +08:00
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#define RT_DEBUG_COLOR
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2021-03-27 15:16:57 +08:00
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//#define RT_DEBUG_MEM (1)
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//#define RT_DEBUG_SCHEDULER (1)
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//#define RT_DEBUG_IPC (1)
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2013-01-08 22:40:58 +08:00
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//#define THREAD_DEBUG
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//#define IRQ_DEBUG
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#define RT_USING_OVERFLOW_CHECK
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//#define DFS_DEBUG
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#define RT_LWIP_DEBUG
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//#define RT_IRQHDL_DEBUG
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//#define RT_USART_DEBUG
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//#define RT_LEUART_DEBUG
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//#define RT_IIC_DEBUG
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//#define RT_MISC_DEBUG
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//#define RT_ADC_DEBUG
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//#define RT_ACMP_DEBUG
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//#define RT_TIMER_DEBUG
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//#define RT_RTC_DEBUG
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#define EFM32_DEBUG
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#define EFM32_EMU_DEBUG
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#define EFM32_ACCEL_DEBUG
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#define EFM32_SFLASH_DEBUG
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//#define EFM32_SDCARD_DEBUG
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#define EFM32_ETHERNET_DEBUG
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#define EFM32_LCD_DEBUG
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#define EFM32_KEYS_DEBUG
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/* Using Hook */
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//#define RT_USING_HOOK
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/* Using Software Timer */
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/* #define RT_USING_TIMER_SOFT */
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2021-03-27 15:16:57 +08:00
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#define RT_TIMER_THREAD_PRIO (4)
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#define RT_TIMER_THREAD_STACK_SIZE (512)
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#define RT_TIMER_TICK_PER_SECOND (10)
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2013-01-08 22:40:58 +08:00
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/* SECTION: IPC */
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/* Using Semaphore*/
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#define RT_USING_SEMAPHORE /* Required by DFS and lwIP */
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/* Using Mutex */
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#define RT_USING_MUTEX /* Required by DFS */
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/* Using Event */
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//#define RT_USING_EVENT
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/* Using MailBox */
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#define RT_USING_MAILBOX /* Required by lwIP */
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/* Using Message Queue */
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#define RT_USING_MESSAGEQUEUE /* Required by RTGUI */
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/* SECTION: Memory Management */
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/* Using Memory Pool Management*/
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//#define RT_USING_MEMPOOL
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/* Using Dynamic Heap Management */
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#define RT_USING_HEAP
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/* Using Small MM */
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#define RT_USING_SMALL_MEM
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/* SECTION: Device System */
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/* Using Device System */
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#define RT_USING_DEVICE
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/* SECTION: UART options */
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/* USART/UART/LEUART Device for Console */
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#if defined(EFM32_G8XX_STK)
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#define RT_USING_USART1 (0x1UL)
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#define RT_USART1_NAME "debug"
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//#define RT_USART1_USING_DMA (0x0UL)
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#elif defined(EFM32_GXXX_DK)
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#define RT_USING_USART1 (0x0UL)
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#define RT_USART1_NAME "debug"
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//#define RT_USART1_USING_DMA (0x0UL)
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#elif defined(EFM32GG_DK3750)
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#define EFM32GG_DK3750_USING_LEUART1
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#if defined(EFM32GG_DK3750_USING_LEUART1)
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#define RT_USING_LEUART1 (0x0UL)
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#define RT_LEUART1_NAME "debug0"
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//#define RT_LEUART1_USING_DMA (0x0UL)
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#else
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#define RT_USING_UART1 (0x2UL)
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#define RT_UART1_NAME "debug"
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//#define RT_UART1_USING_DMA (0x0UL)
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#endif
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#endif
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/* SECTION: SPI options */
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#define EFM32_SPI_MASTER (1 << 0) /* Master mode */
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#define EFM32_SPI_AUTOCS (1 << 1) /* Auto chip select */
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#define EFM32_SPI_9BIT (1 << 2) /* 9-bit data */
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/*
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0: Clock idle low, sample on rising edge
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1: Clock idle low, sample on falling edge
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2: Clock idle high, sample on falling edge
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3: Clock idle high, sample on rising edge.
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*/
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#define EFM32_SPI_CLK_MODE(mode) (mode << 3) /* clock mode */
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#if defined(EFM32_G8XX_STK)
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2021-03-27 15:16:57 +08:00
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//#define RT_USING_USART0 (0x0UL)
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//#define RT_USART0_SYNC_MODE (EFM32_SPI_MASTER)
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//#define RT_USART0_NAME "spi0"
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//#define RT_USART0_USING_DMA (0x1UL)
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2013-01-08 22:40:58 +08:00
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#elif defined(EFM32_GXXX_DK)
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#define RT_USING_USART0 (0x2UL)
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#define RT_USART0_SYNC_MODE (EFM32_SPI_MASTER | EFM32_SPI_AUTOCS | \
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EFM32_SPI_CLK_MODE(0))
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#define RT_USART0_NAME "spi0"
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#define RT_USART0_USING_DMA (0x1UL)
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#define RT_USING_USART2 (0x1UL)
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#define RT_USART2_SYNC_MODE (EFM32_SPI_MASTER | EFM32_SPI_CLK_MODE(0))
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#define RT_USART2_NAME "spi2"
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#define RT_USART2_USING_DMA (0x2UL)
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#elif defined(EFM32GG_DK3750)
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#define RT_USING_USART0 (0x1UL)
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#define RT_USART0_SYNC_MODE (EFM32_SPI_MASTER | EFM32_SPI_AUTOCS | \
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EFM32_SPI_CLK_MODE(0))
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#define RT_USART0_NAME "spi0"
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#define RT_USART0_USING_DMA (0x1UL)
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#define RT_USING_USART1 (0x1UL)
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#define RT_USART1_SYNC_MODE (EFM32_SPI_MASTER | EFM32_SPI_AUTOCS | \
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EFM32_SPI_9BIT | EFM32_SPI_CLK_MODE(3))
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#define RT_USART1_NAME "spi1"
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#define RT_USART1_USING_DMA (0x2UL)
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#endif
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/* SECTION: IIC options */
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2021-03-27 15:16:57 +08:00
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//#define RT_USING_IIC0 0x3UL
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#define RT_IIC0_NAME "iic0"
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2013-01-08 22:40:58 +08:00
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/* SECTION: ACMP options */
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//#define RT_USING_ACMP0
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2021-03-27 15:16:57 +08:00
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#define RT_ACMP0_NAME "acmp0"
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2013-01-08 22:40:58 +08:00
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/* SECTION: ADC options */
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#define RT_USING_ADC0
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2021-03-27 15:16:57 +08:00
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#define RT_ADC0_NAME "adc0"
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2013-01-08 22:40:58 +08:00
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#if defined(RT_USING_ADC0)
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#define RT_USING_MISC
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#endif
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/* SECTION: TIMER options */
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2021-03-27 15:16:57 +08:00
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//#define RT_USING_TIMER2 (0x00) /* Continuous mode */
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#define RT_TIMER2_NAME "tmr2"
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2013-01-08 22:40:58 +08:00
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/* SECTION: RTC options */
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#if (defined(EFM32_G8XX_STK) || defined(EFM32_GXXX_DK) || defined(EFM32GG_DK3750))
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#define RT_USING_RTC
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2021-03-27 15:16:57 +08:00
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#define RT_RTC_NAME "rtc"
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2013-01-08 22:40:58 +08:00
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#endif
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/* SECTION: Serial options */
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#define EFM_USART0 (0x00UL)
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#define EFM_USART1 (0x01UL)
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#define EFM_USART2 (0x02UL)
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#define EFM_UART0 (0x10UL)
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#define EFM_UART1 (0x11UL)
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#define EFM_LEUART0 (0x20UL)
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#define EFM_LEUART1 (0x21UL)
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#if defined(EFM32_G8XX_STK)
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2021-03-27 15:16:57 +08:00
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#define RT_CONSOLE_DEVICE (EFM_USART1)
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2013-01-08 22:40:58 +08:00
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#elif defined(EFM32_GXXX_DK)
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2021-03-27 15:16:57 +08:00
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#define RT_CONSOLE_DEVICE (EFM_USART1)
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2013-01-08 22:40:58 +08:00
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#elif defined(EFM32GG_DK3750)
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#if defined(EFM32GG_DK3750_USING_LEUART1)
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#define RT_CONSOLE_DEVICE (EFM_LEUART1)
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#else
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#define RT_CONSOLE_DEVICE (EFM_UART1)
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#endif
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#endif
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/* SECTION: Runtime library */
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// #define RT_USING_NEWLIB
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2020-09-08 16:42:58 +08:00
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#define RT_LIBC_USING_TIME
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2013-01-08 22:40:58 +08:00
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/* SECTION: Console options */
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#define RT_USING_CONSOLE
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/* the buffer size of console*/
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2021-03-27 15:16:57 +08:00
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#define RT_CONSOLEBUF_SIZE (128)
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2013-01-08 22:40:58 +08:00
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/* SECTION: finsh, a C-Express shell */
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#define RT_USING_FINSH
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/* Using symbol table */
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#define FINSH_USING_SYMTAB
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#define FINSH_USING_DESCRIPTION
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/* SECTION: Peripheral devices */
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2021-03-27 15:16:57 +08:00
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#define EFM32_INTERFACE_ADC (0)
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#define EFM32_INTERFACE_IIC (1)
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#define EFM32_INTERFACE_SPI (2)
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2013-01-08 22:40:58 +08:00
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#if (defined(EFM32_GXXX_DK) || defined(EFM32GG_DK3750))
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2021-03-27 15:16:57 +08:00
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//#define EFM32_USING_ACCEL EFM32_INTERFACE_IIC /* Three axis accelerometer */
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//#define EFM32_USING_SFLASH /* SPI Flash */
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2013-01-08 22:40:58 +08:00
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#define EFM32_USING_SPISD /* MicroSD card */
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//#define EFM32_USING_ETHERNET /* Ethernet controller */
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2013-02-22 23:34:02 +08:00
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//#define EFM32_USING_LCD /* TFT LCD */
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//#define EFM32_USING_KEYS /* Keys and joystick */
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2013-01-08 22:40:58 +08:00
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#endif
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#if defined(EFM32_USING_ACCEL)
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#if (EFM32_USING_ACCEL == EFM32_INTERFACE_ADC)
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2021-03-27 15:16:57 +08:00
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#define ACCEL_USING_DEVICE_NAME RT_ADC0_NAME
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#define ACCEL_USING_DMA (0x3UL) /* For multiple channels scan mode */
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2013-01-08 22:40:58 +08:00
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#elif (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC)
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2021-03-27 15:16:57 +08:00
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#define ACCEL_USING_DEVICE_NAME RT_IIC0_NAME
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2013-01-08 22:40:58 +08:00
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#endif
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#endif
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#if defined(EFM32_USING_SFLASH)
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2021-03-27 15:16:57 +08:00
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#define SFLASH_USING_DEVICE_NAME RT_USART0_NAME
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2013-01-08 22:40:58 +08:00
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#endif
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#if defined(EFM32_USING_SPISD)
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2021-03-27 15:16:57 +08:00
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#define SPISD_USING_DEVICE_NAME RT_USART0_NAME
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#define SPISD_DEVICE_NAME "spiSd"
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2013-01-08 22:40:58 +08:00
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#endif
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#if defined(EFM32_USING_ETHERNET)
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#if defined(EFM32_GXXX_DK)
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2021-03-27 15:16:57 +08:00
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#define ETH_USING_DEVICE_NAME RT_USART2_NAME
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2013-01-08 22:40:58 +08:00
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#elif defined(EFM32GG_DK3750)
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2021-03-27 15:16:57 +08:00
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#define ETH_USING_DEVICE_NAME RT_USART1_NAME
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2013-01-08 22:40:58 +08:00
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#endif
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2021-03-27 15:16:57 +08:00
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#define ETH_DEVICE_NAME "spiEth"
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#define ETH_ADDR_DEFAULT {0x00, 0x01, 0x02, 0x03, 0x04, 0x05}
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2013-01-08 22:40:58 +08:00
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#endif
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/* SECTION: device filesystem */
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#if (defined(RT_USING_NEWLIB) || defined(EFM32_USING_SPISD))
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#define RT_USING_DFS
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/* the max number of mounted filesystem */
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#define DFS_FILESYSTEMS_MAX (2)
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2021-03-27 15:16:57 +08:00
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/* the max number of opened files */
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2013-01-08 22:40:58 +08:00
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#define DFS_FD_MAX (4)
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2021-03-27 15:16:57 +08:00
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/* the max number of cached sector */
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2013-01-08 22:40:58 +08:00
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#define DFS_CACHE_MAX_NUM (4)
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#endif /* defined(RT_USING_NEWLIB) || defined(EFM32_USING_SPISD) */
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#if defined(EFM32_USING_SPISD)
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#define RT_USING_DFS_ELMFAT
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#define DFS_ELMFAT_INTERFACE_EFM
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#endif /* defined(EFM32_USING_SPISD) */
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#if defined(RT_USING_NEWLIB)
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#define RT_USING_DFS_DEVFS
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#endif /* defined(RT_USING_NEWLIB) */
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/* SECTION: lwip, a lighwight TCP/IP protocol stack */
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#if defined(EFM32_USING_ETHERNET)
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#define EFM32_USING_ETH_HTTPD
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//#define EFM32_USING_ETH_UTILS
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2021-03-27 15:16:57 +08:00
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//#define hostName "onelife.dyndns.org"
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//#define userPwdB64 "dXNlcjpwYXNzd2Q="
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2013-01-08 22:40:58 +08:00
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//#define RT_USING_LWIP
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//#define RT_USING_NETUTILS
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//#define RT_LWIP_DHCP
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/* Enable ICMP protocol*/
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#define RT_LWIP_ICMP
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/* Enable ICMP protocol*/
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//#define RT_LWIP_IGMP
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/* Enable UDP protocol*/
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#define RT_LWIP_UDP
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/* Enable TCP protocol*/
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#define RT_LWIP_TCP
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/* Enable DHCP */
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//#define RT_LWIP_DHCP
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/* Enable DNS */
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//#define RT_LWIP_DNS
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/* the number of simulatenously active TCP connections*/
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2021-03-27 15:16:57 +08:00
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#define RT_LWIP_TCP_PCB_NUM (2)
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2013-01-08 22:40:58 +08:00
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/* ip address of target*/
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2021-03-27 15:16:57 +08:00
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#define RT_LWIP_IPADDR0 (192)
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#define RT_LWIP_IPADDR1 (168)
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#define RT_LWIP_IPADDR2 (1)
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#define RT_LWIP_IPADDR3 (118)
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2013-01-08 22:40:58 +08:00
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/* gateway address of target*/
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2021-03-27 15:16:57 +08:00
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#define RT_LWIP_GWADDR0 (192)
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#define RT_LWIP_GWADDR1 (168)
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#define RT_LWIP_GWADDR2 (1)
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#define RT_LWIP_GWADDR3 (1)
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2013-01-08 22:40:58 +08:00
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/* mask address of target*/
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2021-03-27 15:16:57 +08:00
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#define RT_LWIP_MSKADDR0 (255)
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#define RT_LWIP_MSKADDR1 (255)
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#define RT_LWIP_MSKADDR2 (255)
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#define RT_LWIP_MSKADDR3 (0)
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2013-01-08 22:40:58 +08:00
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/* tcp thread options */
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2021-03-27 15:16:57 +08:00
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#define RT_LWIP_TCPTHREAD_PRIORITY (12)
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#define RT_LWIP_TCPTHREAD_MBOX_SIZE (4)
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#define RT_LWIP_TCPTHREAD_STACKSIZE (1024)
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2013-01-08 22:40:58 +08:00
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/* ethernet if thread options */
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2021-03-27 15:16:57 +08:00
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#define RT_LWIP_ETHTHREAD_PRIORITY (15)
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#define RT_LWIP_ETHTHREAD_MBOX_SIZE (4)
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#define RT_LWIP_ETHTHREAD_STACKSIZE (512)
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2013-01-08 22:40:58 +08:00
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#endif /* defined(EFM32_USING_ETHERNET) */
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/* SECTION: RTGUI support */
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#if defined(EFM32_USING_LCD)
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2021-03-27 15:16:57 +08:00
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#define LCD_USING_DEVICE_NAME RT_USART1_NAME
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2013-01-08 22:40:58 +08:00
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#define LCD_DEVICE_NAME "lcd"
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/* using RTGUI support */
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2013-02-21 14:03:34 +08:00
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// #define RT_USING_RTGUI
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2013-01-08 22:40:58 +08:00
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/* name length of RTGUI object */
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#define RTGUI_NAME_MAX (16)
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/* support 16 weight font */
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#define RTGUI_USING_FONT16
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/* support 12 weight font */
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#define RTGUI_USING_FONT12
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/* support Chinese font */
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#define RTGUI_USING_FONTHZ
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/* use DFS as file interface */
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#define RTGUI_USING_DFS_FILERW
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/* use font file as Chinese font */
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/* #define RTGUI_USING_HZ_FILE */
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/* use Chinese bitmap font */
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#define RTGUI_USING_HZ_BMP
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/* use small size in RTGUI */
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/* #define RTGUI_USING_SMALL_SIZE */
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/* use mouse cursor */
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#define RTGUI_USING_MOUSE_CURSOR
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/* RTGUI image options */
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#define RTGUI_IMAGE_XPM
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//#define RTGUI_IMAGE_JPEG
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#define RTGUI_IMAGE_TJPGD
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//#define RTGUI_IMAGE_PNG
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#define RTGUI_IMAGE_BMP
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#endif /* defined(EFM32_USING_LCD) */
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/* Exported functions ------------------------------------------------------- */
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#endif /* __RTTHREAD_CFG_H__ */
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