104 lines
2.4 KiB
C
104 lines
2.4 KiB
C
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-08-04 Emuzit first version
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*/
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#ifndef __CH56X_PWM_H__
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#define __CH56X_PWM_H__
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#include "soc.h"
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#include "ch56x_gpio.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define PWM_DEVICE_NAME "pwmx"
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#define PWM_CHANNELS 4
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#define PWM0_PIN GET_PIN(B, 15)
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#define PWM1_PIN GET_PIN(A, 4)
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#define PWM2_PIN GET_PIN(B, 1)
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#define PWM3_PIN GET_PIN(B, 2)
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union _pwm_ctrl_mod
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{
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uint8_t reg;
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struct
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{
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uint8_t pwm0_out_en : 1; // RW, PWM output enable
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uint8_t pwm1_out_en : 1;
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uint8_t pwm2_out_en : 1;
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uint8_t pwm3_out_en : 1;
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uint8_t pwm0_polar : 1; // RW, PWM output polarity
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uint8_t pwm1_polar : 1;
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uint8_t pwm2_polar : 1;
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uint8_t pwm3_polar : 1;
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};
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};
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#define RB_PWM0_OUT_EN 0x01
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#define RB_PWM1_OUT_EN 0x02
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#define RB_PWM2_OUT_EN 0x04
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#define RB_PWM3_OUT_EN 0x08
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#define RB_PWM0_POLAR 0x10
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#define RB_PWM1_POLAR 0x20
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#define RB_PWM2_POLAR 0x40
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#define RB_PWM3_POLAR 0x80
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#define PWM_OUT_EN_MASK 0x0f
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union _pwm_ctrl_cfg
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{
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uint8_t reg;
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struct
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{
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uint8_t cycle_sel : 1; // RW, PWM cycle select, 0/1 for 256/255
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uint8_t resv_1 : 7;
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};
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};
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#define RB_PWM_CYCLE_SEL 0x01
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#define PWM_CYCLE_SEL_256 0
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#define PWM_CYCLE_SEL_255 1
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/*
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* 0x00 R8_PWM_CTRL_MOD: PWM control register
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* 0x01 R8_PWM_CTRL_CFG: PWM control configuration register
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* 0x02 R8_PWM_CLOCK_DIV: PWM clock divisor register
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* 0x04 R8_PWM0_DATA: PWM0 data holding register
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* 0x05 R8_PWM1_DATA: PWM1 data holding register
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* 0x06 R8_PWM2_DATA: PWM2 data holding register
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* 0x07 R8_PWM3_DATA: PWM3 data holding register
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*/
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struct pwm_registers
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{
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union _pwm_ctrl_mod CTRL_MOD;
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union _pwm_ctrl_cfg CTRL_CFG;
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uint8_t CLOCK_DIV;
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uint8_t resv_3;
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union
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{
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uint32_t R32_PWM_DATA;
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uint8_t PWM_DATA[4];
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struct
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{
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uint8_t PWM0_DATA;
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uint8_t PWM1_DATA;
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uint8_t PWM2_DATA;
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uint8_t PWM3_DATA;
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};
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};
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};
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CHECK_STRUCT_SIZE(struct pwm_registers, 8);
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#ifdef __cplusplus
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}
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#endif
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#endif
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