529 lines
14 KiB
C
529 lines
14 KiB
C
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-04-02 henryhuang the first version
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*/
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#include <rtthread.h>
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#include <rtdevice.h>
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#include <board.h>
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#include <rthw.h>
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#define MM32_PIN(index, rcc, gpio, gpio_index) { 0, RCC_##rcc##Periph_GPIO##gpio, GPIO##gpio, GPIO_Pin_##gpio_index, GPIO_PortSourceGPIO##gpio, GPIO_PinSource##gpio_index}
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#define MM32_PIN_DEFAULT {-1, 0, 0, 0, 0, 0}
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/* MM32 GPIO driver */
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struct pin_index
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{
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int index;
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uint32_t rcc;
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GPIO_TypeDef *gpio;
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uint32_t pin;
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uint8_t port_source;
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uint8_t pin_source;
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};
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static const struct pin_index mm32_pin_map[] =
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{
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MM32_PIN_DEFAULT,
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MM32_PIN_DEFAULT,
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MM32_PIN(2, APB2, C, 13),
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MM32_PIN(3, APB2, C, 14),
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MM32_PIN(4, APB2, C, 15),
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MM32_PIN_DEFAULT,
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MM32_PIN_DEFAULT,
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MM32_PIN_DEFAULT,
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MM32_PIN_DEFAULT,
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MM32_PIN_DEFAULT,
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MM32_PIN(10, APB2, A, 0),
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MM32_PIN(11, APB2, A, 1),
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MM32_PIN(12, APB2, A, 2),
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MM32_PIN(13, APB2, A, 3),
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MM32_PIN(14, APB2, A, 4),
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MM32_PIN(15, APB2, A, 5),
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MM32_PIN(16, APB2, A, 6),
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MM32_PIN(17, APB2, A, 7),
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MM32_PIN(18, APB2, B, 0),
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MM32_PIN(19, APB2, B, 1),
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MM32_PIN(20, APB2, B, 2),
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MM32_PIN(21, APB2, B, 10),
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MM32_PIN(22, APB2, B, 11),
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MM32_PIN_DEFAULT,
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MM32_PIN_DEFAULT,
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MM32_PIN(25, APB2, B, 12),
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MM32_PIN(26, APB2, B, 13),
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MM32_PIN(27, APB2, B, 14),
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MM32_PIN(28, APB2, B, 15),
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MM32_PIN(29, APB2, A, 8),
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MM32_PIN(30, APB2, A, 9),
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MM32_PIN(31, APB2, A, 10),
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MM32_PIN(32, APB2, A, 11),
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MM32_PIN(33, APB2, A, 12),
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MM32_PIN(34, APB2, A, 13),
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MM32_PIN_DEFAULT,
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MM32_PIN_DEFAULT,
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MM32_PIN(37, APB2, A, 14),
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MM32_PIN(38, APB2, A, 15),
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MM32_PIN(39, APB2, B, 3),
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MM32_PIN(40, APB2, B, 4),
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MM32_PIN(41, APB2, B, 5),
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MM32_PIN(42, APB2, B, 6),
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MM32_PIN(43, APB2, B, 7),
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MM32_PIN_DEFAULT,
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MM32_PIN(45, APB2, B, 8),
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MM32_PIN(46, APB2, B, 9),
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MM32_PIN_DEFAULT,
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MM32_PIN_DEFAULT,
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};
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struct pin_irq_map
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{
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rt_uint16_t pinbit;
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rt_uint32_t irqbit;
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enum IRQn irqno;
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};
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const struct pin_irq_map mm32_pin_irq_map[] =
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{
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{GPIO_Pin_0, EXTI_Line0, EXTI0_IRQn },
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{GPIO_Pin_1, EXTI_Line1, EXTI1_IRQn },
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{GPIO_Pin_2, EXTI_Line2, EXTI2_IRQn },
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{GPIO_Pin_3, EXTI_Line3, EXTI3_IRQn },
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{GPIO_Pin_4, EXTI_Line4, EXTI4_IRQn },
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{GPIO_Pin_5, EXTI_Line5, EXTI9_5_IRQn },
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{GPIO_Pin_6, EXTI_Line6, EXTI9_5_IRQn },
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{GPIO_Pin_7, EXTI_Line7, EXTI9_5_IRQn },
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{GPIO_Pin_8, EXTI_Line8, EXTI9_5_IRQn },
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{GPIO_Pin_9, EXTI_Line9, EXTI9_5_IRQn },
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{GPIO_Pin_10, EXTI_Line10, EXTI15_10_IRQn},
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{GPIO_Pin_11, EXTI_Line11, EXTI15_10_IRQn},
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{GPIO_Pin_12, EXTI_Line12, EXTI15_10_IRQn},
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{GPIO_Pin_13, EXTI_Line13, EXTI15_10_IRQn},
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{GPIO_Pin_14, EXTI_Line14, EXTI15_10_IRQn},
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{GPIO_Pin_15, EXTI_Line15, EXTI15_10_IRQn},
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};
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struct rt_pin_irq_hdr mm32_pin_irq_hdr_tab[] =
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{
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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};
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#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
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const struct pin_index *get_pin(uint8_t pin)
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{
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const struct pin_index *index;
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if (pin < ITEM_NUM(mm32_pin_map))
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{
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index = &mm32_pin_map[pin];
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if (index->gpio == 0)
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index = RT_NULL;
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}
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else
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{
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index = RT_NULL;
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}
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return index;
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};
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void mm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
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{
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const struct pin_index *index;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return;
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}
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if (value == PIN_LOW)
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{
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GPIO_ResetBits(index->gpio, index->pin);
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}
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else
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{
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GPIO_SetBits(index->gpio, index->pin);
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}
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}
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int mm32_pin_read(rt_device_t dev, rt_base_t pin)
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{
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int value;
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const struct pin_index *index;
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value = PIN_LOW;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return PIN_LOW;
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}
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if (GPIO_ReadInputDataBit(index->gpio, index->pin) == Bit_RESET)
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{
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value = PIN_LOW;
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}
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else
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{
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value = PIN_HIGH;
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}
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return value;
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}
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void mm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
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{
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const struct pin_index *index;
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GPIO_InitTypeDef GPIO_InitStructure;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return;
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}
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/* GPIO Periph clock enable */
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RCC_APB2PeriphClockCmd(index->rcc, ENABLE);
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/* Configure GPIO_InitStructure */
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GPIO_InitStructure.GPIO_Pin = index->pin;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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if (mode == PIN_MODE_OUTPUT)
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{
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/* output setting */
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
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}
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else if (mode == PIN_MODE_OUTPUT_OD)
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{
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/* output setting: od. */
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD;
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}
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else if (mode == PIN_MODE_INPUT)
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{
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/* input setting: not pull. */
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
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}
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else if (mode == PIN_MODE_INPUT_PULLUP)
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{
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/* input setting: pull up. */
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
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}
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else
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{
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/* input setting:default. */
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
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}
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GPIO_Init( index->gpio, &GPIO_InitStructure);
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}
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rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
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{
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int i;
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for (i = 0; i < 32; i++)
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{
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if ((0x01 << i) == bit)
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{
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return i;
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}
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}
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return -1;
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}
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rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
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{
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rt_int32_t mapindex = bit2bitno(pinbit);
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if (mapindex < 0 || mapindex >= ITEM_NUM(mm32_pin_irq_map))
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{
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return RT_NULL;
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}
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return &mm32_pin_irq_map[mapindex];
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};
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rt_err_t mm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
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rt_uint32_t mode, void (*hdr)(void *args), void *args)
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{
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const struct pin_index *index;
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rt_base_t level;
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rt_int32_t irqindex = -1;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return -RT_ENOSYS;
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}
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irqindex = bit2bitno(index->pin);
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if (irqindex < 0 || irqindex >= ITEM_NUM(mm32_pin_irq_map))
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{
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return -RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (mm32_pin_irq_hdr_tab[irqindex].pin == pin &&
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mm32_pin_irq_hdr_tab[irqindex].hdr == hdr &&
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mm32_pin_irq_hdr_tab[irqindex].mode == mode &&
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mm32_pin_irq_hdr_tab[irqindex].args == args
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)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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if (mm32_pin_irq_hdr_tab[irqindex].pin != -1)
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{
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rt_hw_interrupt_enable(level);
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return -RT_EBUSY;
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}
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mm32_pin_irq_hdr_tab[irqindex].pin = pin;
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mm32_pin_irq_hdr_tab[irqindex].hdr = hdr;
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mm32_pin_irq_hdr_tab[irqindex].mode = mode;
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mm32_pin_irq_hdr_tab[irqindex].args = args;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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rt_err_t mm32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
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{
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const struct pin_index *index;
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rt_base_t level;
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rt_int32_t irqindex = -1;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return RT_ENOSYS;
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}
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irqindex = bit2bitno(index->pin);
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if (irqindex < 0 || irqindex >= ITEM_NUM(mm32_pin_irq_map))
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{
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return RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (mm32_pin_irq_hdr_tab[irqindex].pin == -1)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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mm32_pin_irq_hdr_tab[irqindex].pin = -1;
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mm32_pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
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mm32_pin_irq_hdr_tab[irqindex].mode = 0;
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mm32_pin_irq_hdr_tab[irqindex].args = RT_NULL;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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rt_err_t mm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
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rt_uint32_t enabled)
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{
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const struct pin_index *index;
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const struct pin_irq_map *irqmap;
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rt_base_t level;
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rt_int32_t irqindex = -1;
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GPIO_InitTypeDef GPIO_InitStructure;
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NVIC_InitTypeDef NVIC_InitStructure;
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EXTI_InitTypeDef EXTI_InitStructure;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return -RT_ENOSYS;
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}
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if (enabled == PIN_IRQ_ENABLE)
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{
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irqindex = bit2bitno(index->pin);
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if (irqindex < 0 || irqindex >= ITEM_NUM(mm32_pin_irq_map))
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{
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return -RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (mm32_pin_irq_hdr_tab[irqindex].pin == -1)
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{
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rt_hw_interrupt_enable(level);
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return -RT_ENOSYS;
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}
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irqmap = &mm32_pin_irq_map[irqindex];
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/* GPIO Periph clock enable */
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RCC_APB2PeriphClockCmd(index->rcc, ENABLE);
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/* Configure GPIO_InitStructure */
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GPIO_InitStructure.GPIO_Pin = index->pin;
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|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||
|
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||
|
|
GPIO_Init(index->gpio, &GPIO_InitStructure);
|
||
|
|
|
||
|
|
NVIC_InitStructure.NVIC_IRQChannel = irqmap->irqno;
|
||
|
|
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
|
||
|
|
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
|
||
|
|
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||
|
|
NVIC_Init(&NVIC_InitStructure);
|
||
|
|
|
||
|
|
GPIO_EXTILineConfig(index->port_source, index->pin_source);
|
||
|
|
EXTI_InitStructure.EXTI_Line = irqmap->irqbit;
|
||
|
|
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
|
||
|
|
switch (mm32_pin_irq_hdr_tab[irqindex].mode)
|
||
|
|
{
|
||
|
|
case PIN_IRQ_MODE_RISING:
|
||
|
|
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
|
||
|
|
break;
|
||
|
|
case PIN_IRQ_MODE_FALLING:
|
||
|
|
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
|
||
|
|
break;
|
||
|
|
case PIN_IRQ_MODE_RISING_FALLING:
|
||
|
|
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
|
||
|
|
EXTI_Init(&EXTI_InitStructure);
|
||
|
|
rt_hw_interrupt_enable(level);
|
||
|
|
}
|
||
|
|
else if (enabled == PIN_IRQ_DISABLE)
|
||
|
|
{
|
||
|
|
irqmap = get_pin_irq_map(index->pin);
|
||
|
|
if (irqmap == RT_NULL)
|
||
|
|
{
|
||
|
|
return -RT_ENOSYS;
|
||
|
|
}
|
||
|
|
EXTI_InitStructure.EXTI_Line = irqmap->irqbit;
|
||
|
|
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
|
||
|
|
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
|
||
|
|
EXTI_InitStructure.EXTI_LineCmd = DISABLE;
|
||
|
|
EXTI_Init(&EXTI_InitStructure);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
return -RT_ENOSYS;
|
||
|
|
}
|
||
|
|
|
||
|
|
return RT_EOK;
|
||
|
|
}
|
||
|
|
const static struct rt_pin_ops _mm32_pin_ops =
|
||
|
|
{
|
||
|
|
mm32_pin_mode,
|
||
|
|
mm32_pin_write,
|
||
|
|
mm32_pin_read,
|
||
|
|
mm32_pin_attach_irq,
|
||
|
|
mm32_pin_detach_irq,
|
||
|
|
mm32_pin_irq_enable,
|
||
|
|
};
|
||
|
|
|
||
|
|
int mm32_hw_pin_init(void)
|
||
|
|
{
|
||
|
|
int result;
|
||
|
|
|
||
|
|
result = rt_device_pin_register("pin", &_mm32_pin_ops, RT_NULL);
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
INIT_BOARD_EXPORT(mm32_hw_pin_init);
|
||
|
|
|
||
|
|
rt_inline void pin_irq_hdr(int irqno)
|
||
|
|
{
|
||
|
|
EXTI_ClearITPendingBit(mm32_pin_irq_map[irqno].irqbit);
|
||
|
|
if (mm32_pin_irq_hdr_tab[irqno].hdr)
|
||
|
|
{
|
||
|
|
mm32_pin_irq_hdr_tab[irqno].hdr(mm32_pin_irq_hdr_tab[irqno].args);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
void EXTI0_IRQHandler(void)
|
||
|
|
{
|
||
|
|
/* enter interrupt */
|
||
|
|
rt_interrupt_enter();
|
||
|
|
pin_irq_hdr(0);
|
||
|
|
/* leave interrupt */
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
void EXTI1_IRQHandler(void)
|
||
|
|
{
|
||
|
|
/* enter interrupt */
|
||
|
|
rt_interrupt_enter();
|
||
|
|
pin_irq_hdr(1);
|
||
|
|
/* leave interrupt */
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
void EXTI2_IRQHandler(void)
|
||
|
|
{
|
||
|
|
/* enter interrupt */
|
||
|
|
rt_interrupt_enter();
|
||
|
|
pin_irq_hdr(2);
|
||
|
|
/* leave interrupt */
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
void EXTI3_IRQHandler(void)
|
||
|
|
{
|
||
|
|
/* enter interrupt */
|
||
|
|
rt_interrupt_enter();
|
||
|
|
pin_irq_hdr(3);
|
||
|
|
/* leave interrupt */
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
void EXTI4_IRQHandler(void)
|
||
|
|
{
|
||
|
|
/* enter interrupt */
|
||
|
|
rt_interrupt_enter();
|
||
|
|
pin_irq_hdr(4);
|
||
|
|
/* leave interrupt */
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
void EXTI9_5_IRQHandler(void)
|
||
|
|
{
|
||
|
|
/* enter interrupt */
|
||
|
|
rt_interrupt_enter();
|
||
|
|
if (EXTI_GetITStatus(EXTI_Line5) != RESET)
|
||
|
|
{
|
||
|
|
pin_irq_hdr(5);
|
||
|
|
}
|
||
|
|
if (EXTI_GetITStatus(EXTI_Line6) != RESET)
|
||
|
|
{
|
||
|
|
pin_irq_hdr(6);
|
||
|
|
}
|
||
|
|
if (EXTI_GetITStatus(EXTI_Line7) != RESET)
|
||
|
|
{
|
||
|
|
pin_irq_hdr(7);
|
||
|
|
}
|
||
|
|
if (EXTI_GetITStatus(EXTI_Line8) != RESET)
|
||
|
|
{
|
||
|
|
pin_irq_hdr(8);
|
||
|
|
}
|
||
|
|
if (EXTI_GetITStatus(EXTI_Line9) != RESET)
|
||
|
|
{
|
||
|
|
pin_irq_hdr(9);
|
||
|
|
}
|
||
|
|
/* leave interrupt */
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
void EXTI15_10_IRQHandler(void)
|
||
|
|
{
|
||
|
|
/* enter interrupt */
|
||
|
|
rt_interrupt_enter();
|
||
|
|
if (EXTI_GetITStatus(EXTI_Line10) != RESET)
|
||
|
|
{
|
||
|
|
pin_irq_hdr(10);
|
||
|
|
}
|
||
|
|
if (EXTI_GetITStatus(EXTI_Line11) != RESET)
|
||
|
|
{
|
||
|
|
pin_irq_hdr(11);
|
||
|
|
}
|
||
|
|
if (EXTI_GetITStatus(EXTI_Line12) != RESET)
|
||
|
|
{
|
||
|
|
pin_irq_hdr(12);
|
||
|
|
}
|
||
|
|
if (EXTI_GetITStatus(EXTI_Line13) != RESET)
|
||
|
|
{
|
||
|
|
pin_irq_hdr(13);
|
||
|
|
}
|
||
|
|
if (EXTI_GetITStatus(EXTI_Line14) != RESET)
|
||
|
|
{
|
||
|
|
pin_irq_hdr(14);
|
||
|
|
}
|
||
|
|
if (EXTI_GetITStatus(EXTI_Line15) != RESET)
|
||
|
|
{
|
||
|
|
pin_irq_hdr(15);
|
||
|
|
}
|
||
|
|
/* leave interrupt */
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|