2018-12-10 09:48:01 +08:00
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/*
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2023-01-09 10:20:16 +08:00
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* Copyright (c) 2006-2023, RT-Thread Development Team
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2018-12-10 09:48:01 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-12-05 zylx first version
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2018-12-12 16:49:27 +08:00
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* 2018-12-12 greedyhao Porting for stm32f7xx
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2020-06-23 10:43:18 +08:00
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* 2019-02-01 yuneizhilin fix the stm32_adc_init function initialization issue
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* 2020-06-17 thread-liu Porting for stm32mp1xx
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2020-10-14 15:02:23 +08:00
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* 2020-10-14 Dozingfiretruck Porting for stm32wbxx
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2022-05-29 10:22:33 +08:00
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* 2022-05-22 Stanley Lwin Add stm32_adc_get_vref
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2023-01-02 14:47:58 +08:00
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* 2022-12-26 wdfk-prog Change the order of configuration channels and calibration functions
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2018-12-10 09:48:01 +08:00
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*/
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#include <board.h>
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2018-12-12 16:51:39 +08:00
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#if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3)
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2018-12-10 09:48:01 +08:00
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#include "drv_config.h"
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//#define DRV_DEBUG
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#define LOG_TAG "drv.adc"
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#include <drv_log.h>
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static ADC_HandleTypeDef adc_config[] =
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{
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#ifdef BSP_USING_ADC1
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ADC1_CONFIG,
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#endif
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#ifdef BSP_USING_ADC2
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ADC2_CONFIG,
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#endif
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#ifdef BSP_USING_ADC3
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ADC3_CONFIG,
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#endif
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};
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struct stm32_adc
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{
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ADC_HandleTypeDef ADC_Handler;
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struct rt_adc_device stm32_adc_device;
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};
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static struct stm32_adc stm32_adc_obj[sizeof(adc_config) / sizeof(adc_config[0])];
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2023-04-08 16:07:56 +08:00
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static rt_err_t stm32_adc_get_channel(rt_int8_t rt_channel, uint32_t *stm32_channel)
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{
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switch (rt_channel)
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{
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case 0:
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*stm32_channel = ADC_CHANNEL_0;
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break;
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case 1:
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*stm32_channel = ADC_CHANNEL_1;
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break;
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case 2:
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*stm32_channel = ADC_CHANNEL_2;
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break;
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case 3:
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*stm32_channel = ADC_CHANNEL_3;
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break;
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case 4:
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*stm32_channel = ADC_CHANNEL_4;
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break;
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case 5:
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*stm32_channel = ADC_CHANNEL_5;
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break;
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case 6:
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*stm32_channel = ADC_CHANNEL_6;
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break;
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case 7:
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*stm32_channel = ADC_CHANNEL_7;
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break;
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case 8:
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*stm32_channel = ADC_CHANNEL_8;
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break;
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case 9:
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*stm32_channel = ADC_CHANNEL_9;
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break;
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case 10:
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*stm32_channel = ADC_CHANNEL_10;
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break;
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case 11:
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*stm32_channel = ADC_CHANNEL_11;
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break;
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case 12:
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*stm32_channel = ADC_CHANNEL_12;
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break;
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case 13:
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*stm32_channel = ADC_CHANNEL_13;
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break;
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case 14:
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*stm32_channel = ADC_CHANNEL_14;
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break;
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case 15:
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*stm32_channel = ADC_CHANNEL_15;
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break;
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#ifdef ADC_CHANNEL_16
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case 16:
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*stm32_channel = ADC_CHANNEL_16;
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break;
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#endif /* ADC_CHANNEL_16 */
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case 17:
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*stm32_channel = ADC_CHANNEL_17;
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break;
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#ifdef ADC_CHANNEL_18
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case 18:
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*stm32_channel = ADC_CHANNEL_18;
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break;
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#endif /* ADC_CHANNEL_18 */
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#ifdef ADC_CHANNEL_19
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case 19:
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*stm32_channel = ADC_CHANNEL_19;
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break;
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#endif /* ADC_CHANNEL_19 */
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#ifdef ADC_CHANNEL_VREFINT
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case RT_ADC_INTERN_CH_VREF:
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*stm32_channel = ADC_CHANNEL_VREFINT;
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break;
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#endif /* ADC_CHANNEL_VREFINT */
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#ifdef ADC_CHANNEL_VBAT
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case RT_ADC_INTERN_CH_VBAT:
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*stm32_channel = ADC_CHANNEL_VBAT;
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break;
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#endif /* ADC_CHANNEL_VBAT */
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#ifdef ADC_CHANNEL_TEMPSENSOR
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case RT_ADC_INTERN_CH_TEMPER:
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*stm32_channel = ADC_CHANNEL_TEMPSENSOR;
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break;
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#endif /* ADC_CHANNEL_TEMPSENSOR */
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default:
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return -RT_EINVAL;
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}
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return RT_EOK;
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}
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static rt_err_t stm32_adc_enabled(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled)
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2018-12-10 09:48:01 +08:00
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{
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2019-08-07 14:22:54 +08:00
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ADC_HandleTypeDef *stm32_adc_handler;
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2018-12-10 09:48:01 +08:00
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RT_ASSERT(device != RT_NULL);
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2019-08-07 14:22:54 +08:00
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stm32_adc_handler = device->parent.user_data;
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2018-12-10 09:48:01 +08:00
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if (enabled)
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{
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2023-01-02 14:47:58 +08:00
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ADC_ChannelConfTypeDef ADC_ChanConf;
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rt_memset(&ADC_ChanConf, 0, sizeof(ADC_ChanConf));
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2023-04-08 16:07:56 +08:00
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if(stm32_adc_get_channel(channel, &ADC_ChanConf.Channel) != RT_EOK)
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2023-01-02 14:47:58 +08:00
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{
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2023-04-08 16:07:56 +08:00
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LOG_E("ADC channel illegal: %d", channel);
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return -RT_EINVAL;
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2023-01-02 14:47:58 +08:00
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}
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2023-06-15 21:46:48 +08:00
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#if defined(SOC_SERIES_STM32MP1) || defined (SOC_SERIES_STM32H7) || defined (SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32U5)
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2023-01-02 14:47:58 +08:00
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ADC_ChanConf.Rank = ADC_REGULAR_RANK_1;
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#else
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ADC_ChanConf.Rank = 1;
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#endif
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#if defined(SOC_SERIES_STM32F0)
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ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_71CYCLES_5;
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#elif defined(SOC_SERIES_STM32F1)
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ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_55CYCLES_5;
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#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
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ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_112CYCLES;
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#elif defined(SOC_SERIES_STM32L4)
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ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_247CYCLES_5;
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#elif defined(SOC_SERIES_STM32MP1)
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ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_810CYCLES_5;
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#elif defined(SOC_SERIES_STM32H7)
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ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_810CYCLES_5;
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2023-06-15 21:46:48 +08:00
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#elif defined(SOC_SERIES_STM32U5)
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ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_814CYCLES;
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2023-01-02 14:47:58 +08:00
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#elif defined (SOC_SERIES_STM32WB)
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ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_2CYCLES_5;
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2018-12-10 09:48:01 +08:00
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#endif
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2023-01-02 14:47:58 +08:00
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#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined (SOC_SERIES_STM32WB)
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ADC_ChanConf.Offset = 0;
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#endif
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#if defined(SOC_SERIES_STM32L4)
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ADC_ChanConf.OffsetNumber = ADC_OFFSET_NONE;
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ADC_ChanConf.SingleDiff = LL_ADC_SINGLE_ENDED;
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2023-06-15 21:46:48 +08:00
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#elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined (SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32U5)
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2023-01-02 14:47:58 +08:00
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ADC_ChanConf.OffsetNumber = ADC_OFFSET_NONE; /* ADC channel affected to offset number */
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ADC_ChanConf.Offset = 0;
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ADC_ChanConf.SingleDiff = ADC_SINGLE_ENDED; /* ADC channel differential mode */
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#endif
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2023-06-15 21:46:48 +08:00
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/* enable the analog power domain before configuring channel */
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#if defined(SOC_SERIES_STM32U5)
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__HAL_RCC_PWR_CLK_ENABLE();
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HAL_PWREx_EnableVddA();
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#endif /* defined(SOC_SERIES_STM32U5) */
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2023-01-02 14:47:58 +08:00
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if(HAL_ADC_ConfigChannel(stm32_adc_handler, &ADC_ChanConf) != HAL_OK)
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{
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LOG_E("Failed to configure ADC channel %d", channel);
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}
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/* perform an automatic ADC calibration to improve the conversion accuracy */
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#if defined(SOC_SERIES_STM32L4) || defined (SOC_SERIES_STM32WB)
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if (HAL_ADCEx_Calibration_Start(stm32_adc_handler, ADC_ChanConf.SingleDiff) != HAL_OK)
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{
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LOG_E("ADC calibration error!\n");
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return -RT_ERROR;
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}
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2023-06-15 21:46:48 +08:00
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#elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32U5)
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2023-01-02 14:47:58 +08:00
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/* Run the ADC linear calibration in single-ended mode */
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if (HAL_ADCEx_Calibration_Start(stm32_adc_handler, ADC_CALIB_OFFSET_LINEARITY, ADC_ChanConf.SingleDiff) != HAL_OK)
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{
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LOG_E("ADC open linear calibration error!\n");
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/* Calibration Error */
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return -RT_ERROR;
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}
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#endif
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HAL_ADC_Start(stm32_adc_handler);
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2018-12-10 09:48:01 +08:00
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}
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else
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{
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2023-01-02 14:47:58 +08:00
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HAL_ADC_Stop(stm32_adc_handler);
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2018-12-10 09:48:01 +08:00
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}
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return RT_EOK;
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}
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2022-04-22 22:26:41 +08:00
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static rt_uint8_t stm32_adc_get_resolution(struct rt_adc_device *device)
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{
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2022-06-14 14:17:22 +08:00
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#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F3)
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return 12;
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#else
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ADC_HandleTypeDef *stm32_adc_handler = device->parent.user_data;
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2022-04-22 22:26:41 +08:00
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RT_ASSERT(device != RT_NULL);
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switch(stm32_adc_handler->Init.Resolution)
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{
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2023-01-02 14:47:58 +08:00
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#ifdef SOC_SERIES_STM32H7
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case ADC_RESOLUTION_16B:
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return 16;
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2023-06-15 21:46:48 +08:00
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#endif /* SOC_SERIES_STM32H7 */
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#if defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32U5)
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2023-01-02 14:47:58 +08:00
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case ADC_RESOLUTION_14B:
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return 14;
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2023-06-15 21:46:48 +08:00
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#endif /* defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32U5) */
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2022-04-22 22:26:41 +08:00
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case ADC_RESOLUTION_12B:
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return 12;
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case ADC_RESOLUTION_10B:
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return 10;
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case ADC_RESOLUTION_8B:
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return 8;
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2023-06-15 21:46:48 +08:00
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#if defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32U5)
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2022-04-22 22:26:41 +08:00
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case ADC_RESOLUTION_6B:
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return 6;
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2023-06-15 21:46:48 +08:00
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#endif /* defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32U5) */
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2022-04-22 22:26:41 +08:00
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default:
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return 0;
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}
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2022-06-14 14:17:22 +08:00
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#endif /* defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F3) */
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2022-04-22 22:26:41 +08:00
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}
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2022-05-29 10:22:33 +08:00
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static rt_int16_t stm32_adc_get_vref (struct rt_adc_device *device)
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{
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2023-01-02 14:47:58 +08:00
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if(device == RT_NULL)
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2023-03-17 12:12:16 +08:00
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return -RT_ERROR;
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2023-01-02 14:47:58 +08:00
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rt_uint16_t vref_mv;
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#ifdef __LL_ADC_CALC_VREFANALOG_VOLTAGE
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rt_err_t ret = RT_EOK;
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rt_uint32_t vref_value;
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ADC_HandleTypeDef *stm32_adc_handler = device->parent.user_data;
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2023-04-08 16:07:56 +08:00
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ret = rt_adc_enable(device, RT_ADC_INTERN_CH_VREF);
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2023-03-20 08:40:47 +08:00
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if (ret != RT_EOK) return (rt_int16_t)ret;
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2023-04-08 16:07:56 +08:00
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vref_value = rt_adc_read(device, RT_ADC_INTERN_CH_VREF);
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ret = rt_adc_disable(device, RT_ADC_INTERN_CH_VREF);
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2023-03-20 08:40:47 +08:00
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if (ret != RT_EOK) return (rt_int16_t)ret;
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2023-01-02 14:47:58 +08:00
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2023-04-14 14:07:05 +08:00
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#ifdef SOC_SERIES_STM32U5
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vref_mv = __LL_ADC_CALC_VREFANALOG_VOLTAGE(stm32_adc_handler->Instance, vref_value, stm32_adc_handler->Init.Resolution);
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#else
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2023-01-02 14:47:58 +08:00
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vref_mv = __LL_ADC_CALC_VREFANALOG_VOLTAGE(vref_value, stm32_adc_handler->Init.Resolution);
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2023-04-14 14:07:05 +08:00
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#endif
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2023-01-02 14:47:58 +08:00
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#else
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vref_mv = 3300;
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#endif /* __LL_ADC_CALC_VREFANALOG_VOLTAGE */
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return vref_mv;
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2022-05-29 10:22:33 +08:00
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}
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2023-04-08 16:07:56 +08:00
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static rt_err_t stm32_adc_get_value(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value)
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2018-12-10 09:48:01 +08:00
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{
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2019-08-07 14:22:54 +08:00
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ADC_HandleTypeDef *stm32_adc_handler;
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2018-12-10 09:48:01 +08:00
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(value != RT_NULL);
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2019-08-07 14:22:54 +08:00
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stm32_adc_handler = device->parent.user_data;
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2019-08-06 17:58:36 +08:00
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2018-12-10 09:48:01 +08:00
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/* Wait for the ADC to convert */
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2018-12-26 10:43:16 +08:00
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HAL_ADC_PollForConversion(stm32_adc_handler, 100);
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2018-12-10 09:48:01 +08:00
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/* get ADC value */
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*value = (rt_uint32_t)HAL_ADC_GetValue(stm32_adc_handler);
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return RT_EOK;
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}
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static const struct rt_adc_ops stm_adc_ops =
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{
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.enabled = stm32_adc_enabled,
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2022-04-22 22:26:41 +08:00
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.convert = stm32_adc_get_value,
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.get_resolution = stm32_adc_get_resolution,
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2022-05-29 10:22:33 +08:00
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.get_vref = stm32_adc_get_vref,
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2018-12-10 09:48:01 +08:00
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};
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static int stm32_adc_init(void)
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{
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int result = RT_EOK;
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/* save adc name */
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2019-02-01 12:56:36 +08:00
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char name_buf[5] = {'a', 'd', 'c', '0', 0};
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2018-12-10 09:48:01 +08:00
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int i = 0;
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for (i = 0; i < sizeof(adc_config) / sizeof(adc_config[0]); i++)
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{
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/* ADC init */
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2019-02-01 12:56:36 +08:00
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name_buf[3] = '0';
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2018-12-10 09:48:01 +08:00
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stm32_adc_obj[i].ADC_Handler = adc_config[i];
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2019-02-15 10:43:09 +08:00
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#if defined(ADC1)
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2019-02-01 12:56:36 +08:00
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if (stm32_adc_obj[i].ADC_Handler.Instance == ADC1)
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{
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name_buf[3] = '1';
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}
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2019-02-15 10:43:09 +08:00
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#endif
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#if defined(ADC2)
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2019-02-01 12:56:36 +08:00
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if (stm32_adc_obj[i].ADC_Handler.Instance == ADC2)
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{
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name_buf[3] = '2';
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}
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2019-02-15 10:43:09 +08:00
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#endif
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#if defined(ADC3)
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2019-02-01 12:56:36 +08:00
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if (stm32_adc_obj[i].ADC_Handler.Instance == ADC3)
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{
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name_buf[3] = '3';
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}
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2019-02-15 10:43:09 +08:00
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#endif
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2018-12-10 09:48:01 +08:00
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if (HAL_ADC_Init(&stm32_adc_obj[i].ADC_Handler) != HAL_OK)
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{
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2019-02-01 12:56:36 +08:00
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LOG_E("%s init failed", name_buf);
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2018-12-10 09:48:01 +08:00
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result = -RT_ERROR;
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}
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else
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{
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/* register ADC device */
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if (rt_hw_adc_register(&stm32_adc_obj[i].stm32_adc_device, name_buf, &stm_adc_ops, &stm32_adc_obj[i].ADC_Handler) == RT_EOK)
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{
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2019-02-01 12:56:36 +08:00
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LOG_D("%s init success", name_buf);
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2018-12-10 09:48:01 +08:00
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}
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else
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{
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2019-02-01 12:56:36 +08:00
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LOG_E("%s register failed", name_buf);
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2018-12-10 09:48:01 +08:00
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result = -RT_ERROR;
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}
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}
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}
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return result;
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}
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INIT_BOARD_EXPORT(stm32_adc_init);
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#endif /* BSP_USING_ADC */
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