638 lines
20 KiB
C
638 lines
20 KiB
C
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/******************************************************************************
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*
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* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
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* Copyright (C) 2021 WangHuachen. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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*
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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* @file xil_mpu.c
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*
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* This file provides APIs for enabling/disabling MPU and setting the memory
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* attributes for sections, in the MPU translation table.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- ---------------------------------------------------
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* 5.00 pkp 02/10/14 Initial version
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* 6.2 mus 01/27/17 Updated to support IAR compiler
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* 6.4 asa 08/16/17 Added many APIs for MPU access to make MPU usage
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* user-friendly. The APIs added are: Xil_UpdateMPUConfig,
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* Xil_GetMPUConfig, Xil_GetNumOfFreeRegions,
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* Xil_GetNextMPURegion, Xil_DisableMPURegionByRegNum,
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* Xil_GetMPUFreeRegMask, Xil_SetMPURegionByRegNum, and
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* Xil_InitializeExistingMPURegConfig.
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* Added a new array of structure of type XMpuConfig to
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* represent the MPU configuration table.
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* 6.8 aru 07/02/18 Returned the pointer instead of address
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* of that pointer in Xil_MemMap().
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* </pre>
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*
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*
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******************************************************************************/
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/***************************** Include Files *********************************/
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#include "xil_cache.h"
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#include "xpseudo_asm_gcc.h"
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#include "xil_types.h"
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#include "xil_mpu.h"
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// #include "xdebug.h"
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#include "xreg_cortexr5.h"
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#include "xstatus.h"
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#include <rtthread.h>
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#define DBG_TAG "xil_mpu"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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extern void Xil_DCacheFlush(void);
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extern void Xil_ICacheInvalidate(void);
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extern void Xil_DCacheDisable(void);
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extern void Xil_ICacheDisable(void);
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extern void Xil_DCacheEnable(void);
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extern void Xil_ICacheEnable(void);
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/***************** Macros (Inline Functions) Definitions *********************/
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/**************************** Type Definitions *******************************/
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/************************** Constant Definitions *****************************/
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#define MPU_REGION_SIZE_MIN 0x20
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/************************** Variable Definitions *****************************/
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static const struct {
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u64 size;
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unsigned int encoding;
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}region_size[] = {
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{ 0x20, REGION_32B },
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{ 0x40, REGION_64B },
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{ 0x80, REGION_128B },
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{ 0x100, REGION_256B },
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{ 0x200, REGION_512B },
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{ 0x400, REGION_1K },
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{ 0x800, REGION_2K },
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{ 0x1000, REGION_4K },
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{ 0x2000, REGION_8K },
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{ 0x4000, REGION_16K },
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{ 0x8000, REGION_32K },
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{ 0x10000, REGION_64K },
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{ 0x20000, REGION_128K },
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{ 0x40000, REGION_256K },
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{ 0x80000, REGION_512K },
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{ 0x100000, REGION_1M },
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{ 0x200000, REGION_2M },
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{ 0x400000, REGION_4M },
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{ 0x800000, REGION_8M },
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{ 0x1000000, REGION_16M },
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{ 0x2000000, REGION_32M },
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{ 0x4000000, REGION_64M },
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{ 0x8000000, REGION_128M },
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{ 0x10000000, REGION_256M },
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{ 0x20000000, REGION_512M },
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{ 0x40000000, REGION_1G },
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{ 0x80000000, REGION_2G },
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{ 0x100000000, REGION_4G },
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};
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XMpu_Config Mpu_Config;
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/************************** Function Prototypes ******************************/
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void Xil_InitializeExistingMPURegConfig(void);
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/*****************************************************************************/
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/**
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* @brief This function sets the memory attributes for a section covering
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* 1MB, of memory in the translation table.
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*
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* @param Addr: 32-bit address for which memory attributes need to be set.
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* @param attrib: Attribute for the given memory region.
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* @return None.
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*
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*
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******************************************************************************/
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void Xil_SetTlbAttributes(INTPTR addr, u32 attrib)
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{
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INTPTR Localaddr = addr;
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Localaddr &= (~(0xFFFFFU));
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/* Setting the MPU region with given attribute with 1MB size */
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Xil_SetMPURegion(Localaddr, 0x100000, attrib);
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}
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/*****************************************************************************/
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/**
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* @brief Set the memory attributes for a section of memory in the
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* translation table.
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*
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* @param Addr: 32-bit address for which memory attributes need to be set..
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* @param size: size is the size of the region.
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* @param attrib: Attribute for the given memory region.
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* @return None.
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*
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*
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******************************************************************************/
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u32 Xil_SetMPURegion(INTPTR addr, u64 size, u32 attrib)
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{
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u32 Regionsize = 0;
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INTPTR Localaddr = addr;
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u32 NextAvailableMemRegion;
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unsigned int i;
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NextAvailableMemRegion = Xil_GetNextMPURegion();
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if (NextAvailableMemRegion == 0xFF) {
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LOG_E("No regions available\r\n");
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return XST_FAILURE;
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}
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Xil_DCacheFlush();
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Xil_ICacheInvalidate();
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mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,NextAvailableMemRegion);
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isb();
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/* Lookup the size. */
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for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) {
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if (size <= region_size[i].size) {
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Regionsize = region_size[i].encoding;
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break;
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}
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}
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Localaddr &= ~(region_size[i].size - 1);
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Regionsize <<= 1;
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Regionsize |= REGION_EN;
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dsb();
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mtcp(XREG_CP15_MPU_REG_BASEADDR, Localaddr); /* Set base address of a region */
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mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL, attrib); /* Set the control attribute */
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mtcp(XREG_CP15_MPU_REG_SIZE_EN, Regionsize); /* set the region size and enable it*/
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dsb();
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isb();
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Xil_UpdateMPUConfig(NextAvailableMemRegion, Localaddr, Regionsize, attrib);
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return XST_SUCCESS;
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}
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/*****************************************************************************/
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/**
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* @brief Enable MPU for Cortex R5 processor. This function invalidates I
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* cache and flush the D Caches, and then enables the MPU.
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*
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*
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* @param None.
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* @return None.
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*
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******************************************************************************/
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void Xil_EnableMPU(void)
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{
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u32 CtrlReg, Reg;
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s32 DCacheStatus=0, ICacheStatus=0;
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/* enable caches only if they are disabled */
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#if defined (__GNUC__)
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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#elif defined (__ICCARM__)
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mfcp(XREG_CP15_SYS_CONTROL,CtrlReg);
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#endif
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if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) {
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DCacheStatus=1;
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}
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if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) {
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ICacheStatus=1;
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}
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if(DCacheStatus != 0) {
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Xil_DCacheDisable();
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}
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if(ICacheStatus != 0){
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Xil_ICacheDisable();
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}
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#if defined (__GNUC__)
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Reg = mfcp(XREG_CP15_SYS_CONTROL);
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#elif defined (__ICCARM__)
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mfcp(XREG_CP15_SYS_CONTROL,Reg);
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#endif
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Reg |= 0x00000001U;
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dsb();
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mtcp(XREG_CP15_SYS_CONTROL, Reg);
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isb();
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/* enable caches only if they are disabled in routine*/
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if(DCacheStatus != 0) {
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Xil_DCacheEnable();
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}
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if(ICacheStatus != 0) {
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Xil_ICacheEnable();
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}
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}
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/*****************************************************************************/
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/**
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* @brief Disable MPU for Cortex R5 processors. This function invalidates I
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* cache and flush the D Caches, and then disabes the MPU.
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*
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* @param None.
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*
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* @return None.
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*
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******************************************************************************/
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void Xil_DisableMPU(void)
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{
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u32 CtrlReg, Reg;
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s32 DCacheStatus=0, ICacheStatus=0;
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/* enable caches only if they are disabled */
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#if defined (__GNUC__)
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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#elif defined (__ICCARM__)
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mfcp(XREG_CP15_SYS_CONTROL,CtrlReg);
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#endif
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if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) {
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DCacheStatus=1;
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}
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if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) {
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ICacheStatus=1;
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}
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if(DCacheStatus != 0) {
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Xil_DCacheDisable();
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}
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if(ICacheStatus != 0){
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Xil_ICacheDisable();
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}
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mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0);
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#if defined (__GNUC__)
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Reg = mfcp(XREG_CP15_SYS_CONTROL);
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#elif defined (__ICCARM__)
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mfcp(XREG_CP15_SYS_CONTROL,Reg);
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#endif
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Reg &= ~(0x00000001U);
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dsb();
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mtcp(XREG_CP15_SYS_CONTROL, Reg);
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isb();
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/* enable caches only if they are disabled in routine*/
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if(DCacheStatus != 0) {
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Xil_DCacheEnable();
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}
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if(ICacheStatus != 0) {
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Xil_ICacheEnable();
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}
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}
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/*****************************************************************************/
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/**
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* @brief Update the MPU configuration for the requested region number in
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* the global MPU configuration table.
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*
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* @param reg_num: The requested region number to be updated information for.
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* @param address: 32 bit address for start of the region.
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* @param size: Requested size of the region.
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* @param attrib: Attribute for the corresponding region.
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* @return XST_FAILURE: When the requested region number if 16 or more.
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* XST_SUCCESS: When the MPU configuration table is updated.
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*
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*
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******************************************************************************/
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u32 Xil_UpdateMPUConfig(u32 reg_num, INTPTR address, u32 size, u32 attrib)
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{
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u32 ReturnVal = XST_SUCCESS;
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u32 Tempsize = size;
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u32 Index;
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if (reg_num >= MAX_POSSIBLE_MPU_REGS) {
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LOG_E("Invalid region number\r\n");
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ReturnVal = XST_FAILURE;
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goto exit;
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}
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if (size & REGION_EN) {
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Mpu_Config[reg_num].RegionStatus = MPU_REG_ENABLED;
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Mpu_Config[reg_num].BaseAddress = address;
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Tempsize &= (~REGION_EN);
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Tempsize >>= 1;
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/* Lookup the size. */
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for (Index = 0; Index <
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sizeof region_size / sizeof region_size[0]; Index++) {
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if (Tempsize <= region_size[Index].encoding) {
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Mpu_Config[reg_num].Size = region_size[Index].size;
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break;
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}
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}
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Mpu_Config[reg_num].Attribute = attrib;
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} else {
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Mpu_Config[reg_num].RegionStatus = 0U;
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Mpu_Config[reg_num].BaseAddress = 0U;
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Mpu_Config[reg_num].Size = 0U;
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Mpu_Config[reg_num].Attribute = 0U;
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}
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exit:
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return ReturnVal;
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}
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/*****************************************************************************/
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/**
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* @brief The MPU configuration table is passed to the caller.
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*
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* @param mpuconfig: This is of type XMpu_Config which is an array of
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* 16 entries of type structure representing the MPU config table
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* @return none
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*
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*
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******************************************************************************/
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void Xil_GetMPUConfig (XMpu_Config mpuconfig) {
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u32 Index = 0U;
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while (Index < MAX_POSSIBLE_MPU_REGS) {
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mpuconfig[Index].RegionStatus = Mpu_Config[Index].RegionStatus;
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mpuconfig[Index].BaseAddress = Mpu_Config[Index].BaseAddress;
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mpuconfig[Index].Attribute = Mpu_Config[Index].Attribute;
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|
|
mpuconfig[Index].Size = Mpu_Config[Index].Size;
|
||
|
|
Index++;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*****************************************************************************/
|
||
|
|
/**
|
||
|
|
* @brief Returns the total number of free MPU regions available.
|
||
|
|
*
|
||
|
|
* @param none
|
||
|
|
* @return Number of free regions available to users
|
||
|
|
*
|
||
|
|
*
|
||
|
|
******************************************************************************/
|
||
|
|
u32 Xil_GetNumOfFreeRegions (void) {
|
||
|
|
u32 Index = 0U;
|
||
|
|
int NumofFreeRegs = 0U;
|
||
|
|
|
||
|
|
while (Index < MAX_POSSIBLE_MPU_REGS) {
|
||
|
|
if (MPU_REG_DISABLED == Mpu_Config[Index].RegionStatus) {
|
||
|
|
NumofFreeRegs++;
|
||
|
|
}
|
||
|
|
Index++;
|
||
|
|
}
|
||
|
|
return NumofFreeRegs;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*****************************************************************************/
|
||
|
|
/**
|
||
|
|
* @brief Returns the total number of free MPU regions available in the form
|
||
|
|
* of a mask. A bit of 1 in the returned 16 bit value represents the
|
||
|
|
* corresponding region number to be available.
|
||
|
|
* For example, if this function returns 0xC0000, this would mean, the
|
||
|
|
* regions 14 and 15 are available to users.
|
||
|
|
*
|
||
|
|
* @param none
|
||
|
|
* @return The free region mask as a 16 bit value
|
||
|
|
*
|
||
|
|
*
|
||
|
|
******************************************************************************/
|
||
|
|
u16 Xil_GetMPUFreeRegMask (void) {
|
||
|
|
u32 Index = 0U;
|
||
|
|
u16 FreeRegMask = 0U;
|
||
|
|
|
||
|
|
while (Index < MAX_POSSIBLE_MPU_REGS) {
|
||
|
|
if (MPU_REG_DISABLED == Mpu_Config[Index].RegionStatus) {
|
||
|
|
FreeRegMask |= (1U << Index);
|
||
|
|
}
|
||
|
|
Index++;
|
||
|
|
}
|
||
|
|
return FreeRegMask;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*****************************************************************************/
|
||
|
|
/**
|
||
|
|
* @brief Disables the corresponding region number as passed by the user.
|
||
|
|
*
|
||
|
|
* @param reg_num: The region number to be disabled
|
||
|
|
* @return XST_SUCCESS: If the region could be disabled successfully
|
||
|
|
* XST_FAILURE: If the requested region number is 16 or more.
|
||
|
|
*
|
||
|
|
*
|
||
|
|
******************************************************************************/
|
||
|
|
u32 Xil_DisableMPURegionByRegNum (u32 reg_num) {
|
||
|
|
u32 Temp = 0U;
|
||
|
|
u32 ReturnVal = XST_FAILURE;
|
||
|
|
|
||
|
|
if (reg_num >= 16U) {
|
||
|
|
LOG_E("Invalid region number\r\n");
|
||
|
|
goto exit1;
|
||
|
|
}
|
||
|
|
Xil_DCacheFlush();
|
||
|
|
Xil_ICacheInvalidate();
|
||
|
|
|
||
|
|
mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num);
|
||
|
|
#if defined (__GNUC__)
|
||
|
|
Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN);
|
||
|
|
#elif defined (__ICCARM__)
|
||
|
|
mfcp(XREG_CP15_MPU_REG_SIZE_EN,Temp);
|
||
|
|
#endif
|
||
|
|
Temp &= (~REGION_EN);
|
||
|
|
dsb();
|
||
|
|
mtcp(XREG_CP15_MPU_REG_SIZE_EN,Temp);
|
||
|
|
dsb();
|
||
|
|
isb();
|
||
|
|
Xil_UpdateMPUConfig(reg_num, 0U, 0U, 0U);
|
||
|
|
ReturnVal = XST_SUCCESS;
|
||
|
|
|
||
|
|
exit1:
|
||
|
|
return ReturnVal;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*****************************************************************************/
|
||
|
|
/**
|
||
|
|
* @brief Enables the corresponding region number as passed by the user.
|
||
|
|
*
|
||
|
|
* @param reg_num: The region number to be enabled
|
||
|
|
* @param address: 32 bit address for start of the region.
|
||
|
|
* @param size: Requested size of the region.
|
||
|
|
* @param attrib: Attribute for the corresponding region.
|
||
|
|
* @return XST_SUCCESS: If the region could be created successfully
|
||
|
|
* XST_FAILURE: If the requested region number is 16 or more.
|
||
|
|
*
|
||
|
|
*
|
||
|
|
******************************************************************************/
|
||
|
|
u32 Xil_SetMPURegionByRegNum (u32 reg_num, INTPTR addr, u64 size, u32 attrib)
|
||
|
|
{
|
||
|
|
u32 ReturnVal = XST_SUCCESS;
|
||
|
|
INTPTR Localaddr = addr;
|
||
|
|
u32 Regionsize = 0;
|
||
|
|
u32 Index;
|
||
|
|
|
||
|
|
if (reg_num >= 16U) {
|
||
|
|
LOG_E("Invalid region number\r\n");
|
||
|
|
ReturnVal = XST_FAILURE;
|
||
|
|
goto exit2;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (Mpu_Config[reg_num].RegionStatus == MPU_REG_ENABLED) {
|
||
|
|
LOG_E("Region already enabled\r\n");
|
||
|
|
ReturnVal = XST_FAILURE;
|
||
|
|
goto exit2;
|
||
|
|
}
|
||
|
|
|
||
|
|
Xil_DCacheFlush();
|
||
|
|
Xil_ICacheInvalidate();
|
||
|
|
mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num);
|
||
|
|
isb();
|
||
|
|
|
||
|
|
/* Lookup the size. */
|
||
|
|
for (Index = 0; Index <
|
||
|
|
sizeof region_size / sizeof region_size[0]; Index++) {
|
||
|
|
if (size <= region_size[Index].size) {
|
||
|
|
Regionsize = region_size[Index].encoding;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
Localaddr &= ~(region_size[Index].size - 1);
|
||
|
|
Regionsize <<= 1;
|
||
|
|
Regionsize |= REGION_EN;
|
||
|
|
dsb();
|
||
|
|
mtcp(XREG_CP15_MPU_REG_BASEADDR, Localaddr);
|
||
|
|
mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL, attrib);
|
||
|
|
mtcp(XREG_CP15_MPU_REG_SIZE_EN, Regionsize);
|
||
|
|
dsb();
|
||
|
|
isb();
|
||
|
|
Xil_UpdateMPUConfig(reg_num, Localaddr, Regionsize, attrib);
|
||
|
|
exit2:
|
||
|
|
return ReturnVal;
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
/*****************************************************************************/
|
||
|
|
/**
|
||
|
|
* @brief Initializes the MPU configuration table that are setup in the
|
||
|
|
* R5 boot code in the Init_Mpu function called before C main.
|
||
|
|
*
|
||
|
|
* @param none
|
||
|
|
* @return none
|
||
|
|
*
|
||
|
|
*
|
||
|
|
******************************************************************************/
|
||
|
|
void Xil_InitializeExistingMPURegConfig(void)
|
||
|
|
{
|
||
|
|
u32 Index = 0U;
|
||
|
|
u32 Index1 = 0U;
|
||
|
|
u32 MPURegSize;
|
||
|
|
INTPTR MPURegBA;
|
||
|
|
u32 MPURegAttrib;
|
||
|
|
u32 Tempsize;
|
||
|
|
|
||
|
|
while (Index < MAX_POSSIBLE_MPU_REGS) {
|
||
|
|
mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,Index);
|
||
|
|
#if defined (__GNUC__)
|
||
|
|
MPURegSize = mfcp(XREG_CP15_MPU_REG_SIZE_EN);
|
||
|
|
MPURegBA = mfcp(XREG_CP15_MPU_REG_BASEADDR);
|
||
|
|
MPURegAttrib = mfcp(XREG_CP15_MPU_REG_ACCESS_CTRL);
|
||
|
|
#elif defined (__ICCARM__)
|
||
|
|
mfcp(XREG_CP15_MPU_REG_SIZE_EN,MPURegSize);
|
||
|
|
mfcp(XREG_CP15_MPU_REG_BASEADDR, MPURegBA);
|
||
|
|
mfcp(XREG_CP15_MPU_REG_ACCESS_CTRL, MPURegAttrib);
|
||
|
|
#endif
|
||
|
|
if (MPURegSize & REGION_EN) {
|
||
|
|
Mpu_Config[Index].RegionStatus = MPU_REG_ENABLED;
|
||
|
|
Mpu_Config[Index].BaseAddress = MPURegBA;
|
||
|
|
Mpu_Config[Index].Attribute = MPURegAttrib;
|
||
|
|
Tempsize = MPURegSize & (~REGION_EN);
|
||
|
|
Tempsize >>= 1;
|
||
|
|
for (Index1 = 0; Index1 <
|
||
|
|
(sizeof (region_size) / sizeof (region_size[0])); Index1++) {
|
||
|
|
if (Tempsize <= region_size[Index1].encoding) {
|
||
|
|
Mpu_Config[Index].Size = region_size[Index1].size;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
Index++;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*****************************************************************************/
|
||
|
|
/**
|
||
|
|
* @brief Returns the next available free MPU region
|
||
|
|
*
|
||
|
|
* @param none
|
||
|
|
* @return The free MPU region available
|
||
|
|
*
|
||
|
|
*
|
||
|
|
******************************************************************************/
|
||
|
|
u32 Xil_GetNextMPURegion(void)
|
||
|
|
{
|
||
|
|
u32 Index = 0U;
|
||
|
|
u32 NextAvailableReg = 0xFF;
|
||
|
|
while (Index < MAX_POSSIBLE_MPU_REGS) {
|
||
|
|
if (Mpu_Config[Index].RegionStatus != MPU_REG_ENABLED) {
|
||
|
|
NextAvailableReg = Index;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
Index++;
|
||
|
|
}
|
||
|
|
return NextAvailableReg;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*****************************************************************************/
|
||
|
|
/**
|
||
|
|
* @brief Memory mapping for Cortex r5.
|
||
|
|
*
|
||
|
|
* @param Physaddr is base physical address at which to start mapping.
|
||
|
|
* NULL in Physaddr masks possible mapping errors.
|
||
|
|
* @param size of region to be mapped.
|
||
|
|
* @param flags used to set translation table.
|
||
|
|
*
|
||
|
|
* @return Physaddr on success, NULL on error. Ambiguous if Physaddr==NULL
|
||
|
|
*
|
||
|
|
* @note: u32overflow() is defined for readability and (for __GNUC__) to
|
||
|
|
* - force the type of the check to be the same as the first argument
|
||
|
|
* - hide the otherwise unused third argument of the builtin
|
||
|
|
* - improve safety by choosing the explicit _uadd_ version.
|
||
|
|
* Consider __builtin_add_overflow_p() when available.
|
||
|
|
* Use an alternative (less optimal?) for compilers w/o the builtin.
|
||
|
|
*
|
||
|
|
******************************************************************************/
|
||
|
|
#ifdef __GNUC__
|
||
|
|
#define u32overflow(a, b) ({typeof(a) s; __builtin_uadd_overflow(a, b, &s); })
|
||
|
|
#else
|
||
|
|
#define u32overflow(a, b) ((a) > ((a) + (b)))
|
||
|
|
#endif /* __GNUC__ */
|
||
|
|
void *Xil_MemMap(UINTPTR Physaddr, size_t size, u32 flags)
|
||
|
|
{
|
||
|
|
size_t Regionsize = MPU_REGION_SIZE_MIN;
|
||
|
|
UINTPTR Basephysaddr = 0, end = Physaddr + size;
|
||
|
|
|
||
|
|
if (!flags)
|
||
|
|
return (void *)Physaddr;
|
||
|
|
if (u32overflow(Physaddr, size))
|
||
|
|
return NULL;
|
||
|
|
for ( ; Regionsize != 0; Regionsize <<= 1) {
|
||
|
|
if (Regionsize >= size) {
|
||
|
|
Basephysaddr = Physaddr & ~(Regionsize - 1);
|
||
|
|
if (u32overflow(Basephysaddr, Regionsize))
|
||
|
|
break;
|
||
|
|
if ((Basephysaddr + Regionsize) >= end)
|
||
|
|
return Xil_SetMPURegion(Basephysaddr,
|
||
|
|
Regionsize, flags) == XST_SUCCESS ?
|
||
|
|
(void *)Physaddr : NULL;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return NULL;
|
||
|
|
}
|