2017-07-28 21:34:18 +08:00
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/*
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2021-03-17 02:26:35 +08:00
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* Copyright (c) 2006-2021, RT-Thread Development Team
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2017-07-28 21:34:18 +08:00
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*
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2018-10-22 11:02:14 +08:00
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* SPDX-License-Identifier: Apache-2.0
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2017-07-28 21:34:18 +08:00
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*
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* Change Logs:
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* Date Author Notes
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* 2017-07-28 Tanek the first version
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*/
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#include <rtthread.h>
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#include "usart.h"
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#include "peri_driver.h"
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#ifdef RT_USING_UART
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#ifdef RT_USING_DEVICE
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#include <rtdevice.h>
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#endif
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#define UART_RX_BUFSZ 8
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2017-07-29 14:57:36 +08:00
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/* LPC8XX uart driver */
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struct lpc8xx_uart
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2017-07-28 21:34:18 +08:00
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{
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struct rt_device parent;
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struct rt_ringbuffer rx_rb;
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LPC_USART_T * uart_base;
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IRQn_Type uart_irq;
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rt_uint8_t rx_buffer[UART_RX_BUFSZ];
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2021-03-17 02:26:35 +08:00
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2017-07-28 21:34:18 +08:00
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};
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#ifdef RT_USING_UART0
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2017-07-29 14:57:36 +08:00
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struct lpc8xx_uart uart0_device;
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2017-07-28 21:34:18 +08:00
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#endif
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#ifdef RT_USING_UART1
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2017-07-29 14:57:36 +08:00
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struct lpc8xx_uart uart1_device;
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2017-07-28 21:34:18 +08:00
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#endif
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#ifdef RT_USING_UART2
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2017-07-29 14:57:36 +08:00
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struct lpc8xx_uart uart2_device;
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2017-07-28 21:34:18 +08:00
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#endif
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2017-07-29 14:57:36 +08:00
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void uart_irq_handler(struct lpc8xx_uart* uart)
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2017-07-28 21:34:18 +08:00
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{
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uint32_t status;
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2021-03-17 02:26:35 +08:00
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2017-07-28 21:34:18 +08:00
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/* enter interrupt */
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rt_interrupt_enter();
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2021-03-17 02:26:35 +08:00
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2017-07-28 21:34:18 +08:00
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status = Chip_UART_GetStatus(uart->uart_base);
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if(status & UART_STAT_RXRDY) // RXIRQ
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{
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rt_ringbuffer_putchar_force(&(uart->rx_rb), (rt_uint8_t)Chip_UART_ReadByte(uart->uart_base));
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/* invoke callback */
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if(uart->parent.rx_indicate != RT_NULL)
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{
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uart->parent.rx_indicate(&uart->parent, rt_ringbuffer_data_len(&uart->rx_rb));
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2021-03-17 02:26:35 +08:00
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}
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2017-07-28 21:34:18 +08:00
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}
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2021-03-17 02:26:35 +08:00
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2017-07-28 21:34:18 +08:00
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#ifdef RT_USING_UART0
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void UART0_IRQHandler(void)
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{
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uart_irq_handler(&uart0_device);
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}
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#endif
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#ifdef RT_USING_UART1
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void UART1_IRQHandler(void)
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{
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uart_irq_handler(&uart1_device);
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}
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#endif
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#ifdef RT_USING_UART2
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void UART2_IRQHandler(void)
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{
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uart_irq_handler(&uart2_device);
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}
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#endif
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static void uart1_io_init(LPC_USART_T * uart_base)
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{
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/* Enable the clock to the Switch Matrix */
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2021-03-17 02:26:35 +08:00
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Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SWM);
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2017-07-28 21:34:18 +08:00
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Chip_Clock_SetUARTClockDiv(1);
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2021-03-17 02:26:35 +08:00
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2017-07-28 21:34:18 +08:00
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#ifdef RT_USING_UART0
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if (uart_base == LPC_USART0)
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{
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2021-03-17 02:26:35 +08:00
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Chip_SWM_MovablePinAssign(SWM_U0_TXD_O, 4);
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Chip_SWM_MovablePinAssign(SWM_U0_RXD_I, 0);
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2017-07-28 21:34:18 +08:00
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}
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else
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#endif
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#ifdef RT_USING_UART1
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if (uart_base == LPC_USART1)
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{
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2021-03-17 02:26:35 +08:00
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Chip_SWM_MovablePinAssign(SWM_U1_TXD_O, 4);
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Chip_SWM_MovablePinAssign(SWM_U1_RXD_I, 0);
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2017-07-28 21:34:18 +08:00
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}
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else
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#endif
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#ifdef RT_USING_UART2
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if (uart_base == LPC_USART2)
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{
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2021-03-17 02:26:35 +08:00
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Chip_SWM_MovablePinAssign(SWM_U2_TXD_O, 4);
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Chip_SWM_MovablePinAssign(SWM_U2_RXD_I, 0);
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2017-07-28 21:34:18 +08:00
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}
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else
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#endif
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{
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RT_ASSERT((uart_base == USART0) || (uart_base == USART2) || (uart_base == USART2));
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}
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2021-03-17 02:26:35 +08:00
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/* Disable the clock to the Switch Matrix to save power */
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Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_SWM);
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2017-07-28 21:34:18 +08:00
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}
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static void uart_ll_init(LPC_USART_T * uart)
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{
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Chip_UART_Init(uart);
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Chip_UART_ConfigData(uart, UART_CFG_DATALEN_8 | UART_CFG_PARITY_NONE | UART_CFG_STOPLEN_1);
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2021-03-17 02:26:35 +08:00
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Chip_Clock_SetUSARTNBaseClockRate((115200 * 6 * 16), true);
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Chip_UART_SetBaud(uart, 115200);
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Chip_UART_Enable(uart);
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Chip_UART_TXEnable(uart);
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// we must NOT enable TX ready/idle IRQ before we want to write data
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// otherwise the IRQs will happen as soon as Uart IRQ is enabled in NVIC
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Chip_UART_IntDisable(uart, UART_INTEN_TXRDY | UART_INTEN_TXIDLE);
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Chip_UART_IntEnable(uart, UART_INTEN_RXRDY);
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2017-07-28 21:34:18 +08:00
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}
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static rt_err_t rt_uart_init (rt_device_t dev)
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{
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2017-07-29 14:57:36 +08:00
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struct lpc8xx_uart* uart;
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2017-07-28 21:34:18 +08:00
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RT_ASSERT(dev != RT_NULL);
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2017-07-29 14:57:36 +08:00
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uart = (struct lpc8xx_uart *)dev;
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2021-03-17 02:26:35 +08:00
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2017-07-28 21:34:18 +08:00
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uart1_io_init(uart->uart_base);
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uart_ll_init(uart->uart_base);
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return RT_EOK;
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}
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static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
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{
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2017-07-29 14:57:36 +08:00
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struct lpc8xx_uart* uart;
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2017-07-28 21:34:18 +08:00
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RT_ASSERT(dev != RT_NULL);
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2017-07-29 14:57:36 +08:00
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uart = (struct lpc8xx_uart *)dev;
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2017-07-28 21:34:18 +08:00
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if (dev->flag & RT_DEVICE_FLAG_INT_RX)
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{
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/* Enable the UART Interrupt */
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NVIC_EnableIRQ(uart->uart_irq);
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}
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return RT_EOK;
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}
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static rt_err_t rt_uart_close(rt_device_t dev)
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{
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2017-07-29 14:57:36 +08:00
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struct lpc8xx_uart* uart;
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2017-07-28 21:34:18 +08:00
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RT_ASSERT(dev != RT_NULL);
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2017-07-29 14:57:36 +08:00
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uart = (struct lpc8xx_uart *)dev;
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2017-07-28 21:34:18 +08:00
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if (dev->flag & RT_DEVICE_FLAG_INT_RX)
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{
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/* Disable the UART Interrupt */
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NVIC_DisableIRQ(uart->uart_irq);
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}
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return RT_EOK;
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}
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2023-02-06 07:35:33 +08:00
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static rt_ssize_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
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2017-07-28 21:34:18 +08:00
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{
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/* interrupt receive */
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rt_base_t level;
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rt_size_t length;
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2017-07-29 14:57:36 +08:00
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struct lpc8xx_uart* uart;
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2017-07-28 21:34:18 +08:00
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RT_ASSERT(serial != RT_NULL);
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2017-07-29 14:57:36 +08:00
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uart = (struct lpc8xx_uart *)dev;
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2017-07-28 21:34:18 +08:00
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RT_ASSERT(uart != RT_NULL);
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/* disable interrupt */
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level = rt_hw_interrupt_disable();
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length = rt_ringbuffer_get(&(uart->rx_rb), buffer, size);
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/* enable interrupt */
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rt_hw_interrupt_enable(level);
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return length;
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}
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2023-02-06 07:35:33 +08:00
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static rt_ssize_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
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2017-07-28 21:34:18 +08:00
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{
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char *ptr = (char*) buffer;
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2017-07-29 14:57:36 +08:00
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struct lpc8xx_uart* uart;
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2017-07-28 21:34:18 +08:00
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RT_ASSERT(serial != RT_NULL);
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2017-07-29 14:57:36 +08:00
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uart = (struct lpc8xx_uart *)dev;
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2017-07-28 21:34:18 +08:00
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if (dev->open_flag & RT_DEVICE_FLAG_STREAM)
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{
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/* stream mode */
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while (size)
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{
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if (*ptr == '\n')
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{
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while (!(Chip_UART_GetStatus(uart->uart_base) & UART_STAT_TXRDY));
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2021-03-17 02:26:35 +08:00
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Chip_UART_SendByte(uart->uart_base, '\r');
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2017-07-28 21:34:18 +08:00
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}
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while (!(Chip_UART_GetStatus(uart->uart_base) & UART_STAT_TXRDY));
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2021-03-17 02:26:35 +08:00
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Chip_UART_SendByte(uart->uart_base, *ptr);
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2017-07-28 21:34:18 +08:00
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ptr ++;
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size --;
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}
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}
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else
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{
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while (size)
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{
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while (!(Chip_UART_GetStatus(uart->uart_base) & UART_STAT_TXRDY));
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2021-03-17 02:26:35 +08:00
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Chip_UART_SendByte(uart->uart_base, *ptr);
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2017-07-28 21:34:18 +08:00
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ptr++;
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size--;
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}
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}
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return (rt_size_t) ptr - (rt_size_t) buffer;
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}
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int rt_hw_usart_init(void)
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{
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#ifdef RT_USING_UART0
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{
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2017-07-29 14:57:36 +08:00
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struct lpc8xx_uart* uart;
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2017-07-28 21:34:18 +08:00
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/* get uart device */
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uart = &uart1_device;
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/* device initialization */
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uart->parent.type = RT_Device_Class_Char;
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uart->uart_base = LPC_USART0;
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uart->uart_irq = UART0_IRQn;
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2021-03-17 02:26:35 +08:00
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2017-07-28 21:34:18 +08:00
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rt_ringbuffer_init(&(uart->rx_rb), uart->rx_buffer, sizeof(uart->rx_buffer));
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/* device interface */
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2021-03-17 02:26:35 +08:00
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uart->parent.init = rt_uart_init;
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uart->parent.open = rt_uart_open;
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2017-07-28 21:34:18 +08:00
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uart->parent.close = rt_uart_close;
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2021-03-17 02:26:35 +08:00
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uart->parent.read = rt_uart_read;
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2017-07-28 21:34:18 +08:00
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uart->parent.write = rt_uart_write;
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uart->parent.control = RT_NULL;
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uart->parent.user_data = RT_NULL;
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rt_device_register(&uart->parent, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
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}
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#endif
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2021-03-17 02:26:35 +08:00
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2017-07-28 21:34:18 +08:00
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#ifdef RT_USING_UART1
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{
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2017-07-29 14:57:36 +08:00
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struct lpc8xx_uart* uart;
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2017-07-28 21:34:18 +08:00
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/* get uart device */
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uart = &uart1_device;
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/* device initialization */
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uart->parent.type = RT_Device_Class_Char;
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uart->uart_base = LPC_USART1;
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uart->uart_irq = UART1_IRQn;
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2021-03-17 02:26:35 +08:00
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2017-07-28 21:34:18 +08:00
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rt_ringbuffer_init(&(uart->rx_rb), uart->rx_buffer, sizeof(uart->rx_buffer));
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/* device interface */
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2021-03-17 02:26:35 +08:00
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uart->parent.init = rt_uart_init;
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uart->parent.open = rt_uart_open;
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2017-07-28 21:34:18 +08:00
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uart->parent.close = rt_uart_close;
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2021-03-17 02:26:35 +08:00
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uart->parent.read = rt_uart_read;
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2017-07-28 21:34:18 +08:00
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uart->parent.write = rt_uart_write;
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uart->parent.control = RT_NULL;
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uart->parent.user_data = RT_NULL;
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rt_device_register(&uart->parent, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
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}
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#endif
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#ifdef RT_USING_UART2
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{
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2017-07-29 14:57:36 +08:00
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struct lpc8xx_uart* uart;
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2017-07-28 21:34:18 +08:00
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/* get uart device */
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uart = &uart2_device;
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/* device initialization */
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uart->parent.type = RT_Device_Class_Char;
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uart->uart_base = LPC_USART1;
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uart->uart_irq = UART2_IRQn;
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rt_ringbuffer_init(&(uart->rx_rb), uart->rx_buffer, sizeof(uart->rx_buffer));
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/* device interface */
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2021-03-17 02:26:35 +08:00
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uart->parent.init = rt_uart_init;
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uart->parent.open = rt_uart_open;
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2017-07-28 21:34:18 +08:00
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uart->parent.close = rt_uart_close;
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2021-03-17 02:26:35 +08:00
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uart->parent.read = rt_uart_read;
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2017-07-28 21:34:18 +08:00
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uart->parent.write = rt_uart_write;
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uart->parent.control = RT_NULL;
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uart->parent.user_data = RT_NULL;
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rt_device_register(&uart->parent, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
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}
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#endif /* RT_USING_UART2 */
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return 0;
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}
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INIT_BOARD_EXPORT(rt_hw_usart_init);
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#endif /*RT_USING_UART*/
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