202 lines
6.7 KiB
C
202 lines
6.7 KiB
C
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//###########################################################################
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//
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// FILE: F2837xD_Cla_defines.h
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//
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// TITLE: #defines used in CLA examples
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//
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//###########################################################################
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// $TI Release: F2837xD Support Library v3.05.00.00 $
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// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
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// $Copyright:
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// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef F2837xD_CLA_DEFINES_H
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#define F2837xD_CLA_DEFINES_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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//
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// Defines
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//
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//
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// MCTL Register
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//
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#define CLA_FORCE_RESET 0x1
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#define CLA_IACK_ENABLE 0x1
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#define CLA_IACK_DISABLE 0x0
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//
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// MMEMCFG Register
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//
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#define CLA_CLA_SPACE 0x1
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#define CLA_CPU_SPACE 0x0
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//
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// MIER Interrupt Enable Register
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//
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#define CLA_INT_ENABLE 0x1
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#define CLA_INT_DISABLE 0x0
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//
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// Peripheral Interrupt Source Select define for DMAnCLASourceSelect Register
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//
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#define CLA_TRIG_NOPERPH 0
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#define CLA_TRIG_ADCAINT1 1
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#define CLA_TRIG_ADCAINT2 2
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#define CLA_TRIG_ADCAINT3 3
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#define CLA_TRIG_ADCAINT4 4
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#define CLA_TRIG_ADCAEVT 5
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#define CLA_TRIG_ADCBINT1 6
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#define CLA_TRIG_ADCBINT2 7
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#define CLA_TRIG_ADCBINT3 8
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#define CLA_TRIG_ADCBINT4 9
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#define CLA_TRIG_ADCBEVT 10
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#define CLA_TRIG_ADCCINT1 11
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#define CLA_TRIG_ADCCINT2 12
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#define CLA_TRIG_ADCCINT3 13
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#define CLA_TRIG_ADCCINT4 14
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#define CLA_TRIG_ADCCEVT 15
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#define CLA_TRIG_ADCDINT1 16
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#define CLA_TRIG_ADCDINT2 17
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#define CLA_TRIG_ADCDINT3 18
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#define CLA_TRIG_ADCDINT4 19
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#define CLA_TRIG_ADCDEVT 20
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#define CLA_TRIG_XINT1 29
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#define CLA_TRIG_XINT2 30
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#define CLA_TRIG_XINT3 31
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#define CLA_TRIG_XINT4 32
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#define CLA_TRIG_XINT5 33
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#define CLA_TRIG_EPWM1INT 36
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#define CLA_TRIG_EPWM2INT 37
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#define CLA_TRIG_EPWM3INT 38
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#define CLA_TRIG_EPWM4INT 39
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#define CLA_TRIG_EPWM5INT 40
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#define CLA_TRIG_EPWM6INT 41
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#define CLA_TRIG_EPWM7INT 42
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#define CLA_TRIG_EPWM8INT 43
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#define CLA_TRIG_EPWM9INT 44
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#define CLA_TRIG_EPWM10INT 45
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#define CLA_TRIG_EPWM11INT 46
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#define CLA_TRIG_EPWM12INT 47
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#define CLA_TRIG_TINT0 68
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#define CLA_TRIG_TINT1 69
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#define CLA_TRIG_TINT2 70
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#define CLA_TRIG_MXEVTA 71
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#define CLA_TRIG_MREVTA 72
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#define CLA_TRIG_MXEVTB 73
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#define CLA_TRIG_MREVTB 74
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#define CLA_TRIG_ECAP1INT 75
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#define CLA_TRIG_ECAP2INT 76
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#define CLA_TRIG_ECAP3INT 77
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#define CLA_TRIG_ECAP4INT 78
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#define CLA_TRIG_ECAP5INT 79
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#define CLA_TRIG_ECAP6INT 80
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#define CLA_TRIG_EQEP1INT 83
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#define CLA_TRIG_EQEP2INT 84
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#define CLA_TRIG_EQEP3INT 85
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#define CLA_TRIG_HRCAP1INT 87
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#define CLA_TRIG_HRCAP2INT 88
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#define CLA_TRIG_SD1INT 95
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#define CLA_TRIG_SD2INT 96
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#define CLA_TRIG_UPP1_INT 107
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#define CLA_TRIG_SPITXINTA 109
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#define CLA_TRIG_SPIRXINTA 110
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#define CLA_TRIG_SPITXINTB 111
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#define CLA_TRIG_SPIRXINTB 112
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#define CLA_TRIG_SPITXINTC 113
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#define CLA_TRIG_SPIRXINTC 114
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#define Cla1ForceTask1andWait()asm(" IACK #0x0001"); \
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asm(" RPT #3 || NOP"); \
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while(Cla1Regs.MIRUN.bit.INT1 == 1);
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#define Cla1ForceTask2andWait()asm(" IACK #0x0002"); \
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asm(" RPT #3 || NOP"); \
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while(Cla1Regs.MIRUN.bit.INT2 == 1);
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#define Cla1ForceTask3andWait()asm(" IACK #0x0004"); \
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asm(" RPT #3 || NOP"); \
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while(Cla1Regs.MIRUN.bit.INT3 == 1);
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#define Cla1ForceTask4andWait()asm(" IACK #0x0008"); \
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asm(" RPT #3 || NOP"); \
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while(Cla1Regs.MIRUN.bit.INT4 == 1);
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#define Cla1ForceTask5andWait()asm(" IACK #0x0010"); \
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asm(" RPT #3 || NOP"); \
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while(Cla1Regs.MIRUN.bit.INT5 == 1);
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#define Cla1ForceTask6andWait()asm(" IACK #0x0020"); \
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asm(" RPT #3 || NOP"); \
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while(Cla1Regs.MIRUN.bit.INT6 == 1);
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#define Cla1ForceTask7andWait()asm(" IACK #0x0040"); \
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asm(" RPT #3 || NOP"); \
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while(Cla1Regs.MIRUN.bit.INT7 == 1);
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#define Cla1ForceTask8andWait()asm(" IACK #0x0080"); \
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asm(" RPT #3 || NOP"); \
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while(Cla1Regs.MIRUN.bit.INT8 == 1);
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#define Cla1ForceTask1() asm(" IACK #0x0001")
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#define Cla1ForceTask2() asm(" IACK #0x0002")
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#define Cla1ForceTask3() asm(" IACK #0x0004")
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#define Cla1ForceTask4() asm(" IACK #0x0008")
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#define Cla1ForceTask5() asm(" IACK #0x0010")
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#define Cla1ForceTask6() asm(" IACK #0x0020")
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#define Cla1ForceTask7() asm(" IACK #0x0040")
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#define Cla1ForceTask8() asm(" IACK #0x0080")
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#ifdef __cplusplus
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}
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#endif
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#endif // - end of F2837xD_CLA_DEFINES_H
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//
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// End of file
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//
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